Datasheet

Functional Description
50 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.2.1 Supported PCIe* Port Configurations
PCI Express Root Ports 1–4 or Ports 5–8 can independently be configured as four x1s,
two x2s, one x2 and two x1s, or one x4 port widths, as shown in Ta b l e 3 - 1 and
Tab l e 3- 2 .
Function disable is covered in Section 5.1.63.
3.2.2 Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs,
when enabled.
When an interrupt is generated using the legacy pin, the pin is internally routed to
Intel® Xeon® Processor D-1500 Product Family interrupt controllers. The pin that is
driven is based upon the setting of the chipset configuration registers. Specifically, the
chipset configuration registers used are the D28IP (Base address + 310Ch) and D28IR
(Base address + 3146h) registers.
Tab l e 3- 3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the Hot-Plug and PME interrupt bits.
Table 3-1. PCI Express* Ports 1 thru 4 - Supported Configurations
Port 1Port 2Port 3Port 4
x4
x2 x2
x2 x1 x1
x1 x1 x1 x1
Table 3-2. PCI Express* Ports 5 thru 8 - Supported Configurations
Port 5Port 6Port 7Port 8
x4
x2 x2
x2 x1 x1
x1 x1 x1 x1
Table 3-3. MSI versus PCI IRQ Actions
Interrupt Register Wire-Mode Action MSI Action
All bits 0 Wire inactive No action
One or more bits set to 1 Wire active Send message
One or more bits set to 1, new bit gets set to 1 Wire active Send message
One or more bits set to 1, software clears some (but not all) bits Wire active Send message
One or more bits set to 1, software clears all bits Wire inactive No action
Software clears one or more bits, and one or more bits are set on
the same clock
Wire active Send message