Datasheet
Intel® Xeon® Processor D-1500 Product Family 5
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.17.12 Function Level Reset Support (FLR) ...............................................................143
3.17.13 USB Overcurrent Protection ..........................................................................143
3.18 Integrated USB 2.0 Rate Matching Hub ......................................................................144
3.18.1 Overview ...................................................................................................144
3.18.2 Architecture ...............................................................................................144
3.19 xHCI Controller (D20:F0) .........................................................................................145
3.20 SMBus Controller (D31:F3) ......................................................................................145
3.20.1 Host Controller ...........................................................................................146
3.20.2 Bus Arbitration............................................................................................150
3.20.3 Bus Timing .................................................................................................151
3.20.4 Interrupts / SMI#........................................................................................151
3.20.5 SMBALERT# ...............................................................................................152
3.20.6 SMBus CRC Generation and Checking.............................................................152
3.20.7 SMBus Slave Interface .................................................................................152
3.21 Thermal Management..............................................................................................158
3.21.1 Thermal Sensor ..........................................................................................158
3.21.2 Intel® Xeon® Processor D-1500 Product Family Thermal Throttling................... 160
3.21.3 Thermal Reporting Over System Management Link 1 Interface (SMLink0) ...........161
3.22 Intel
®
Management Engine (Intel
®
ME) and Intel
®
Management Engine Firmware
(Intel
®
ME FW) 9.0 .................................................................................................166
3.22.1 Intel
®
Management Engine (Intel
®
ME) Requirements .....................................167
3.23 Serial Peripheral Interface (SPI)................................................................................168
3.23.1 SPI Supported Feature Overview ...................................................................169
3.23.2 Flash Descriptor ..........................................................................................170
3.23.3 Flash Access...............................................................................................172
3.23.4 Serial Flash Device Compatibility Requirements ...............................................173
3.23.5 Multiple Page Write Usage Model ...................................................................176
3.23.6 Flash Device Configurations ..........................................................................177
3.23.7 SPI Flash Device Recommended Pinout ..........................................................177
3.23.8 Serial Flash Device Package..........................................................................178
3.23.9 PWM Outputs..............................................................................................179
3.23.10 TACH Inputs ...............................................................................................179
3.24 Feature Capability Mechanism ..................................................................................179
3.25 Intel
®
Virtualization Technology (Intel
®
VT) ...............................................................180
3.25.1 Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O (Intel
®
VT-
d) Objectives ..............................................................................................180
3.25.2 Intel
®
VT-d Features Supported ....................................................................180
3.25.3 Support for Function Level Reset (FLR) in Intel® Xeon® Processor D-
1500 Product Family....................................................................................180
3.25.4 Virtualization Support for Intel® Xeon® Processor D-1500 Product Family
IOxAPIC.....................................................................................................181
3.25.5 Virtualization Support for High Precision Event Timer (HPET).............................181
4 Register and Memory Mapping .......................................................................................182
4.1 PCI Devices and Functions .......................................................................................183
4.2 PCI Configuration Map .............................................................................................184
4.3 I/O Map.................................................................................................................184
4.3.1 Fixed I/O Address Ranges ............................................................................184
4.3.2 Variable I/O Decode Ranges .........................................................................186
4.4 Memory Map ..........................................................................................................187
4.4.1 Boot-Block Update Scheme...........................................................................189
5 Chipset Configuration Registers.....................................................................................191
5.1 Chipset Configuration Registers (Memory Space).........................................................191
5.1.1 RPC—Root Port Configuration Register ...........................................................192
5.1.2 RPFN—Root Port Function Number and Hide for PCI Express* Root Ports
Register .....................................................................................................192
5.1.3 FLRSTAT—Function Level Reset Pending Status Register...................................194
5.1.4 TRSR—Trap Status Register..........................................................................194
5.1.5 TRCR—Trapped Cycle Register ......................................................................194
5.1.6 TWDR—Trapped Write Data Register..............................................................195
5.1.7 IOTRn—I/O Trap Register (0–3) ....................................................................195
5.1.8 V0CTL—Virtual Channel 0 Resource Control Register ........................................195
5.1.9 V0STS—Virtual Channel 0 Resource Status Register.........................................196
5.1.10 V1CTL—Virtual Channel 1 Resource Control Register ........................................196
5.1.11 V1STS—Virtual Channel 1 Resource Status Register.........................................196