Datasheet

PCI Express* Configuration Registers
498 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12 Compliance De-Emphasis (CD) — R/W.
This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter
Compliance bit being 1b.
Encodings:
0 = -6 dB
1 = -3.5 dB
When the Link is operating at 2.5 GT/s, the setting of this bit has no effect.
The default value of this bit is 0b.
This bit is intended for debug, compliance testing purposes. System firmware and software are
allowed to modify this bit only during debug or compliance testing.
11 Compliance SOS (CSOS) — R/W.
When set to 1b, the LTSSM is required to send SKP Ordered Sets periodically in between the
(modified) compliance patterns.
The default value of this bit is 0b.
10 Enter Modified Compliance (EMC) — R/W.
When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters
Polling.Compliance substrate. This register is intended for debug, compliance testing purposes only
and the system must ensure it is set to the default value during normal operation.
The default value of this bit is 0b.
9:7 Transmit Margin (TM) — R/W. This field controls the value of the non-de-emphasized voltage level
at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration
substrate (see PCI Express Chapter 4 for details of how the Transmitter voltage level is determined
in various states).
Encodings:
000b: Normal operating range
001b: 800-1200 mV for full swing and 400-700 mV for half-swing
010b - (n-1): Values must be monotonic with a non-zero slope. The value of n must be greater than
3 and less than 7. At least two of these must be below the normal operating range of n: 200–400 mV
for full-swing and 100–200 mV for half-swing
n - 111b” Reserved
For a Multi-Function device associated with an Upstream Port, the field in Function 0 is of type RWS,
and only Function 0 controls the component‘s Link behavior. In all other Functions of that device, this
field is of type RsvdP.
Default value of this field is 000b.
Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 000b. This
register is intended for debug, compliance testing purposes only and the system must ensure it is set
to the default value during normal operation.
6 Selectable De-emphasis (SD) — R/W.
When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an
Upstream component.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, the setting of this bit has no effect.
5 Reserved
4 Enter Compliance (EC) — R/W.
Software is permitted to force a Link to enter Compliance mode at the speed indicated in the Target
Link Speed field by setting this bit to 1b in both components on a Link and then initiating a hot reset
on the Link.
3:0 Target Link Speed (TLS)— R/W. This field sets an upper limit on Link operational speed by
restricting the values advertised by the upstream component in its training sequences.
0001b = 2.5 GT/s Target Link Speed
0010b = 5.0 GT/s and 2.5 GT/s Target Link Speeds
All other values reserved.
Bit Description