Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 497
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.37 DCTL2—Device Control 2 Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 68h–69h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
13.1.38 LCTL2—Link Control 2 Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 70h–71h Attribute: R/W
Default Value: 0002h Size: 16 bits
Bit Description
15:11 Reserved
10 LTR Mechanism Enable (LTREN) — RW. A value of 1b enables support for the optional Latency
Tolerance Reporting (LTR) mechanism.
9:5 Reserved
4 Completion Timeout Disable (CTD) — R/W. When set to 1b, this bit disables the Completion
Timeout mechanism.
If there are outstanding requests when the bit is cleared, it is permitted but not required for
hardware to apply the completion timeout mechanism to the outstanding requests. If this is done, it
is permitted to base the start time for each request on either the time this bit was cleared or the
time each request was issued.
3:0 Completion Timeout Value (CTV) — R/W. In Devices that support Completion Timeout
programmability, this field allows system software to modify the Completion Timeout value. This field
is applicable to Root Ports, Endpoints that issue requests on their own behalf, and PCI Express* to
PCI/PCI-X Bridges that take ownership of requests issued on PCI Express. For all other devices this
field is reserved and must be hardwired to 0000b.
A Device that does not support this optional capability must hardwire this field to 0000b and is
required to implement a timeout value in the range 50 us to 50 ms. Devices that support Completion
Timeout programmability must support the values given below, corresponding to the
programmability ranges indicated in the Completion Timeout Values Supported field. Intel® Xeon®
Processor D-1500 Product Family targeted configurable ranges are listed below, along with the
range allowed by the PCI Express 2.0 specification.
Defined encodings:
0000b = Default range: 40 ms to 50 ms (specification range 50 us to 50 ms)
Values available if Range A (50 us to 10 ms) programmability range is supported:
0001b = 90 μs to 100 μs (specification range is 50 μs to 100 μs)
0010b = 9 ms to 10ms (specification range is 1 ms to 10 ms)
Values available if Range B (10 ms to 250 ms) programmability range is supported:
0101b = 40 ms to 50 ms (specification range is 16 ms to 55 ms)
0110b = 160 ms to 170 ms (specification range is 65 ms to 210 ms)
Values available if Range C (250 ms to 4s) programmability range is supported:
1001b = 400 ms to 500 ms (specification range is 260 ms to 900 ms)
1010b = 1.6s to 1.7s (specification range is 1s to 3.5s)
All other values are Reserved.
Note: Software is permitted to change the value in this field at any time. For requests already
pending when the Completion Timeout Value is changed, hardware is permitted to use
either the new or the old value for the outstanding requests, and is permitted to base the
start time for each request either on when this value was changed or on when each request
was issued.
Bit Description
15:13 Reserved