Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 495
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.33 SLSTS—Slot Status Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 5Ah–5Bh Attribute: R/WC, RO
Default Value: 0000h Size: 16 bits
13.1.34 RCTL—Root Control Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 5Ch–5Dh Attribute: R/W
Default Value: 0000h Size: 16 bits
3 Presence Detect Changed Enable (PDE) — R/W.
0 = Hot-Plug interrupts based on presence detect logic changes is disabled.
1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence detect logic
changes state.
2:0 Reserved
Bit Description
Bit Description
15:9 Reserved
8 Link Active State Changed (LASC) — R/WC.
1 = This bit is set when the value reported in Data Link Layer Link Active field of the Link Status
register (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is changed. In response to a Data Link
Layer State Changed event, software must read Data Link Layer Link Active field of the Link
Status register to determine if the link is active before initiating configuration cycles to the hot
plugged device.
7Reserved
6 Presence Detect State (PDS) — RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5/F6/F7:42h:bit 8) is set
(indicating that this root port spawns a slot), then this bit:
0 = Indicates the slot is empty.
1 = Indicates the slot has a device connected.
Otherwise, if XCAP.SI is cleared, this bit is always set (1).
5 MRL Sensor State (MS) — Reserved as the MRL sensor is not implemented.
4 Reserved
3 Presence Detect Changed (PDC) — R/WC.
0 = No change in the PDS bit.
1 = The PDS bit changed states.
2 MRL Sensor Changed (MSC) — Reserved as the MRL sensor is not implemented.
1 Power Fault Detected (PFD) — Reserved as a power controller is not implemented.
0Reserved
Bit Description
15:4 Reserved
3 PME Interrupt Enable (PIE) — R/W.
0 = Interrupt generation disabled.
1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0~F7:60h, bit 16) is in a set
state (either due to a 0 to 1 transition, or due to this bit being set with RSTS.IS already set).
2 System Error on Fatal Error Enable (SFE) — R/W.
0 = An SERR# will not be generated.
1 = An SERR# will be generated, assuming CMD.SEE (D28:F0~F7:04, bit 8) is set, if a fatal error is
reported by any of the devices in the hierarchy of this root port, including fatal errors in this
root port.