Datasheet

PCI Express* Configuration Registers
494 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.31 SLCAP—Slot Capabilities Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 54h–57h Attribute: R/WO, RO
Default Value: 00060060h Size: 32 bits
13.1.32 SLCTL—Slot Control Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 58h–59h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
3:0 Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI Express*
link.
0001b = Link is 2.5 Gb/s
0010b = Link is 5.0 Gb/s
Bit Description
Bit Description
31:19 Physical Slot Number (PSN) — R/WO. This is a value that is unique to the slot number. BIOS sets
this field and it remains set until a platform reset.
18:17 Reserved
16:15 Slot Power Limit Scale (SLS) — R/WO. Specifies the scale used for the slot power limit value.
BIOS sets this field and it remains set until a platform reset.
14:7 Slot Power Limit Value (SLV) — R/WO. Specifies the upper limit (in conjunction with SLS value),
on the upper limit on power supplied by the slot. The two values together indicate the amount of
power in watts allowed for the slot. BIOS sets this field and it remains set until a platform reset.
6 Hot-Plug Capable (HPC) — R/WO.
1b = Indicates that Hot-Plug is supported.
5 Hot-Plug Surprise (HPS) — R/WO.
1b = Indicates the device may be removed from the slot without prior notification.
4 Power Indicator Present (PIP) — RO.
0b = Indicates that a power indicator LED is not present for this slot.
3 Attention Indicator Present (AIP) — RO.
0b = Indicates that an attention indicator LED is not present for this slot.
2 MRL Sensor Present (MSP) — RO.
0b = Indicates that an MRL sensor is not present.
1 Power Controller Present (PCP) — RO.
0b = Indicates that a power controller is not implemented for this slot.
0 Attention Button Present (ABP) — RO.
0b = Indicates that an attention button is not implemented for this slot.
Bit Description
15:13 Reserved
12 Link Active Changed Enable (LACE) — R/W. When set, this field enables generation of a Hot-Plug
interrupt when the Data Link Layer Link Active field (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is
changed.
11 Reserved
10 Power Controller Control (PCC) — RO.This bit has no meaning for module based Hot-Plug.
9:6 Reserved
5 Hot-Plug Interrupt Enable (HPE) — R/W.
0 = Hot-Plug interrupts based on Hot-Plug events is disabled.
1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events.
4 Reserved