Datasheet
PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 493
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.30 LSTS—Link Status Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 52h–53h Attribute: RO
Default Value: See bit description Size: 16 bits
5 Retrain Link (RL) — R/W.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
Note: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5/F6/F7:52, bit 11) to check the status of
training.
Note: It is permitted to write 1b to this bit while simultaneously writing modified values to other
fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting
Link training must use the modified values. If the LTSSM is already in Recovery or
Configuration, the modified values are not required to affect the Link training that is already
in progress.
4 Link Disable (LD) — R/W.
0 = Link enabled.
1 = The root port will disable the link.
3 Read Completion Boundary Control (RCBC) — RO. Indicates the read completion boundary is 64
bytes.
2Reserved
1:0 Active State Link PM Control (APMC) — R/W. Indicates whether the root port should enter L0s or
L1 or both.
00 = Disabled
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled
Bit Description
Bit Description
15:14 Reserved
13 Data Link Layer Active (DLLA) — RO. Default value is 0b.
0 = Data Link Control and Management State Machine is not in the DL_Active state
1 = Data Link Control and Management State Machine is in the DL_Active state
12 Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that Intel® Xeon® Processor D-1500
Product Family uses the same reference clock as on the platform and does not generate its own
clock.
11 Link Training (LT) — RO. Default value is 0b.
0 = Link training completed.
1 = Link training is occurring.
10 Link Training Error (LTE) — RO. Not supported. Set value is 0b.
9:4 Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the given PCI
Express* link. The contents of this NLW field is undefined if the link has not successfully trained.
Note: 000001b = x1 link width, 000010b =x2 linkwidth, 000100b = x4 linkwidth
Port # Possible Values
1 000001b, 000010b, 000100b
2 000001b
3 000001b, 000010b
4 000001b
5 000001b, 000010b, 000100b
6 000001b
7 000001b, 000010b
8 000001b