Datasheet
PCI Express* Configuration Registers
492 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.29 LCTL—Link Control Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 50h–51h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
11:10 Active State Power Management Support (APMS) — R/WO. Indicates what level of active state
link power management is supported on the root port.
9:4 Maximum Link Width (MLW) — RO/V.
These bits are set by the PCIEPCS1[1:0] soft strap in the PCHSTRP9 record.
Note: Support for 1 x2 or 1 x4 configuration on PCIe Port 1 is only available per Section 3.1
guidelines.
000011 = 1 x4: Port 1 (x4)
000010 = Reserved
000001 = 1 x2 and 2 x1s: Port 1 (x2), Port 3 (x1) and Port 4 (x1)
000000 = 4 x1s: Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1)
This bit is set by the PCIEPCS2[1:0] soft strap in the PCHSTRP9 record.
000011 = 1 x4: Port 5 (x4)
000010 = Reserved
000001 = 1 x2 and 2 x1s: Port 5 (x2), Port 7 (x1) and Port 8 (x1)
000000 = 4 x1s: Port 5 (x1), Port 6 (x1), Port 7 (x1) and Port 8 (x1)
3:0 Maximum Link Speed (MLS) — RO.
0001b = indicates the link speed is 2.5 Gb/s
0010b = 5.0 Gb/s and 2.5Gb/s link speeds supported
Note: These bits report a value of 0001b if Gen2 disable bit 14 is set in the MPC register, else the
value reported is 0010b
Bit Description
Value Definition
00b Reserved
01b L0s Entry Supported
10b Reserved
11b Both L0s and L1 Entry Supported
Bit Description
15:10 Reserved
9 Hardware Autonomous Width Disable – RO. Hardware never attempts to change the link width
except when attempting to correct unreliable Link operation.
8 Reserved
7 Extended Synch (ES) — R/W.
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to
entering L0.
6 Common Clock Configuration (CCC) — R/W.
0 = Intel® Xeon® Processor D-1500 Product Family and device are not using a common reference
clock.
1 = Intel® Xeon® Processor D-1500 Product Family and device are operating with a distributed
common reference clock.