Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 489
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.25 DCAP—Device Capabilities Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 44h–47h Attribute: R/WO, RO
Default Value: 00008000h Size: 32 bits
13.1.26 DCTL—Device Control Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 48h–49h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
31:28 Reserved
27:26 Captured Slot Power Limit Scale (CSPS) — RO. Not supported.
25:18 Captured Slot Power Limit Value (CSPV) — RO. Not supported.
17:16 Reserved
15 Role Based Error Reporting (RBER) — RO. Indicates that this device implements the functionality
defined in the Error Reporting ECN as required by the PCI Express 2.0 specification.
14:12 Reserved
11:9 Endpoint L1 Acceptable Latency (E1AL) — RO. This field is reserved with a setting of 000b for
devices other than Endpoints, per the PCI Express 2.0 Spec.
8:6 Endpoint L0 Acceptable Latency (E0AL) — RO. This field is reserved with a setting of 000b for
devices other than Endpoints, per the PCI Express 2.0 Spec.
5 Extended Tag Field Supported (ETFS) — RO. Indicates that 8-bit tag fields are supported.
4:3 Phantom Functions Supported (PFS) — RO. No phantom functions supported.
2:0 Max Payload Size Supported (MPS) — RWO. BIOS should write to this field during system
initialization. Only a maximum payload size of 128B is supported. Programming this field to any
value other than 000b (128B) will result in aliasing to 128B max payload size.
Bit Description
15 Reserved
14:12 Max Read Request Size (MRRS) — RO. Hardwired to 0.
11 Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-snoop requests.
10 Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device connected has
detected aux power. It has no effect on the root port otherwise.
9 Phantom Functions Enable (PFE) — RO. Not supported.
8 Extended Tag Field Enable (ETFE) — RO. Not supported.
7:5 Max Payload Size (MPS) — R/W. The root port only supports 128B max payloads, regardless of
the programming of this field. Programming this field to any value other than 000b (128B) will result
in aliasing to 128B max payload size. BIOS should program this field prior to enabling BME.
4 Enable Relaxed Ordering (ERO) — RO. Not supported.
3 Unsupported Request Reporting Enable (URE) — R/W.
0 = The root port will ignore unsupported request errors.
1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when
detecting an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked
Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the Root
Control Register when an uncorrectable non-Advisory UR is received with the severity set by the
Uncorrectable Error Severity register.
2 Fatal Error Reporting Enable (FEE) — R/W.
0 = The root port will ignore fatal errors.
1 = Enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or
error messages received across the link. Other bits also control the full scope of related error
reporting.