Datasheet

PCI Express* Configuration Registers
488 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.23 CLIST—Capabilities List Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 40–41h Attribute: R/WO, RO
Default Value: 8010h Size: 16 bits
13.1.24 XCAP—PCI Express* Capabilities Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 42h–43h Attribute: R/WO, RO
Default Value: 0042h Size: 16 bits
4 VGA 16-Bit Decode (V16) — R/W.
0 = VGA range is enabled.
1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled, and only
the base I/O ranges can be decoded.
3 VGA Enable (VE)— R/W.
0 = The ranges below will not be claimed off the backbone by the root port.
1 = The following ranges will be claimed off the backbone by the root port:
• Memory ranges A0000h-BFFFFh
• I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination of 1s
2 ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and
I/O Limit registers and are in the first 64 KB of PCI I/O space.
0 = The root port will not block any forwarding from the backbone as described below.
1 = The root port will block any forwarding from the backbone to the device of I/O transactions
addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh).
1 SERR# Enable (SE) — R/W.
0 = The messages described below are not forwarded to the backbone.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to the backbone.
0 Parity Error Response Enable (PERE) — R/W. When set,
0 = Poisoned write TLPs and completions indicating poisoned TLPs will not set the SSTS.DPD
(D28:F0/F1/F2/F3/F4/F5/F6/F7:1E, bit 8).
1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the SSTS.DPD (D28:F0/
F1/F2/F3/F4/F5/F6/F7:1E, bit 8).
Bit Description
Bit Description
15:8 Next Capability (NEXT) — RWO. Indicates the location of the next pointer. The default value of this
register is 80h, which points to the MSI Capability structure. Since this is a RWO register, BIOS must
write a value to this register, even if it is to re-write the default value.
7:0 Capability ID (CID) — RO. Indicates this is a PCI Express* capability.
Bit Description
15:14 Reserved
13:9 Interrupt Message Number (IMN) — RO. Intel® Xeon® Processor D-1500 Product Family does
not have multiple MSI interrupt numbers.
8 Slot Implemented (SI) — R/WO. Indicates whether the root port is connected to a slot. Slot
support is platform specific. BIOS programs this field, and it is maintained until a platform reset.
7:4 Device / Port Type (DT) — RO. Indicates this is a PCI Express* root port.
3:0 Capability Version (CV) — RO. Indicates PCI Express 2.0.