Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 487
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.20 CAPP—Capabilities List Pointer Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 34h Attribute: RWO
Default Value: 40h Size: 8 bits
13.1.21 INTR—Interrupt Information Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: See bit description Size: 16 bits
Function Level Reset:No (Bits 7:0 only)
13.1.22 BCTRL—Bridge Control Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 3Eh–3Fh Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
7:0 Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the capabilities
list is at 40h in configuration space.
Bit Description
15:8 Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the root port. At reset, this
register takes on the following values that reflect the reset state of the D28IP register in chipset
config space:
Note: The value that is programmed into D28IP is always reflected in this register.
7:0 Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate which interrupt
line (vector) the interrupt is connected to. No hardware action is taken on this register. These bits
are not reset by FLR.
Port Reset Value
1 D28IP.P1IP
2 D28IP.P2IP
3 D28IP.P3IP
4 D28IP.P4IP
5 D28IP.P5IP
6 D28IP.P6IP
7 D28IP.P7IP
8 D28IP.P8IP
Bit Description
15:12 Reserved
11 Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification, Revision 1.0a
10 Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision 1.0a.
9 Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification, Revision 1.0a.
8 Primary Discard Timer (PDT): Reserved per PCI Express* Base Specification, Revision 1.0a.
7 Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification, Revision 1.0a.
6 Secondary Bus Reset (SBR) — R/W. Triggers a hot reset on the PCI Express* port.
5 Master Abort Mode (MAM): Reserved per Express specification.