Datasheet

PCI Express* Configuration Registers

486 Intel® Xeon® Processor D-1500 Product Family

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

13.1.17 PMBL—Prefetchable Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)

Address Offset: 24h–27h Attribute: R/W, RO

Default Value: 00010001h Size: 32 bits

Accesses that are within the ranges specified in this register will be sent to the device if

CMD.MSE (D28:F0~F7;04, bit 1) is set. Accesses from the device that are outside the

ranges specified will be forwarded to the backbone if CMD.BME (D28:F0~F7;04, bit 2)

is set. The comparison performed is PMBU32:PMB ≥ AD[63:32]:AD[31:20] ≤

PMLU32:PML.

13.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits

Address Offset: 28h–2Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

13.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Address Offset: 2Ch–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

19:16 Reserved

15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming address to

determine the lower 1-MB aligned value of the range.

3:0 Reserved

Bit Description

31:20 Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20 of the

incoming address to determine the upper 1-MB aligned value of the range.

19:16 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing

15:4 Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20 of the

incoming address to determine the lower 1-MB aligned value of the range.

3:0 64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing

Bit Description

31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the prefetchable

address base.

Bit Description

31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the prefetchable

address limit.