Datasheet
PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 485
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.15 SSTS—Secondary Status Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 1Eh–1Fh Attribute: R/WC
Default Value: 0000h Size: 16 bits
13.1.16 MBL—Memory Base and Limit Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 20h–23h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Accesses that are within the ranges specified in this register will be sent to the attached
device if CMD.MSE (D28:F0~F7:04:bit 1) is set. Accesses from the attached device that
are outside the ranges specified will be forwarded to the backbone if CMD.BME
(D28:F0~F7:04:bit 2) is set. The comparison performed is MB ≥ AD[31:20] ≤ ML.
11:8 I/O Limit Address Capability (IOLC)
— RO. Indicates that the bridge does not support 32-bit I/
O addressing.
7:4 I/O Base Address (IOBA)
— R/W.
I/O Base bits corresponding to address lines 15:12 for 4-KB
alignment. Bits 11:0 are assumed to be padded to 000h.
3:0 I/O Base Address Capability (IOBC)
— RO. Indicates that the bridge does not support 32-bit I/
O addressing.
Bit Description
Bit Description
15 Detected Parity Error (DPE) — R/WC.
0 = No error.
1 = The port received a poisoned TLP.
14 Received System Error (RSE) — R/WC.
0 = No error.
1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device.
13 Received Master Abort (RMA) — R/WC.
0 = Unsupported Request not received.
1 = The port received a completion with “Unsupported Request” status from the device.
12 Received Target Abort (RTA) — R/WC.
0 = Completion Abort not received.
1 = The port received a completion with “Completion Abort” status from the device.
11 Signaled Target Abort (STA) — R/WC.
0 = Completion Abort not sent.
1 = The port generated a completion with “Completion Abort” status to the device.
10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base Specification.
8 Data Parity Error Detected (DPD) — R/WC.
0 = Conditions below did not occur.
1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3/F4/F5:3E: bit 0) is set, and either of the following
two conditions occurs:
• Port receives completion marked poisoned.
• Port poisons a write request to the secondary side.
7 Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base Specification.
6Reserved
5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification.
4:0 Reserved
Bit Description
31:20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming address to
determine the upper 1-MB aligned value of the range.