Datasheet

PCI Express* Configuration Registers
484 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.10 PLT—Primary Latency Timer Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
13.1.11 HEADTYP—Header Type Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Eh Attribute: RO
Default Value: 81h Size: 8 bits
13.1.12 BNUM—Bus Number Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 18–1Ah Attribute: R/W
Default Value: 000000h Size: 24 bits
13.1.13 SLT—Secondary Latency Timer Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 1Bh Attribute: RO
Default Value: 00h Size: 8 bits
13.1.14 IOBL—I/O Base and Limit Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 1Ch–1Dh Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
7:3 Latency Count. Reserved per the PCI Express* Base Specification.
2:0 Reserved
Bit Description
7 Multi-Function Device — RO.
0 = Single-function device.
1 = Multi-function device.
6:0 Configuration Layout— RO. This field is determined by bit 2 of the MPC register (D28:F0-5:Offset
D8h, bit 2).
00h = Indicates a Host Bridge.
01h = Indicates a PCI-to-PCI bridge.
Bit Description
23:16 Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the
bridge.
15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number the port.
7:0 Primary Bus Number (PBN) — R/W. Indicates the bus number of the backbone.
Bit Description
7:0 Secondary Latency Timer — Reserved for a Root Port per the PCI Express* Base Specification.
Bit Description
15:12 I/O Limit Address (IOLA) — R/W.
I/O Base bits corresponding to address lines 15:12 for 4-KB
alignment. Bits 11:0 are assumed to be padded to FFFh.