Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 483
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.5 RID—Revision Identification Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
13.1.6 PI—Programming Interface Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
13.1.7 SCC—Sub Class Code Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 0Ah Attribute: RO
Default Value: 04h Size: 8 bits
13.1.8 BCC—Base Class Code Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Bh Attribute: RO
Default Value: 06h Size: 8 bits
13.1.9 CLS—Cache Line Size Register (PCI Express*—D28:F0/F1/
F2/F3/F4/F5/F6/F7)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0 Revision ID — RO. This field indicates the device specific revision identifier.
Bit Description
7:0 Programming Interface — RO.
00h = No specific register level programming interface defined.
Bit Description
7:0 Sub Class Code (SCC) — RO. This field is determined by bit 2 of the MPC register (D28:F0-5:Offset
D8h, bit 2).
04h = PCI-to-PCI bridge.
00h = Host Bridge.
Bit Description
7:0 Base Class Code (BCC) — RO.
06h = Indicates the device is a bridge device.
Bit Description
7:0 Cache Line Size (CLS) — R/W. This is read/write but contains no functionality, per the PCI
Express* Base Specification.