Datasheet

PCI Express* Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 481
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
13.1.1 VID—Vendor Identification Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
13.1.2 DID—Device Identification Register (PCI Express*—
D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 02h–03h Attribute: RO
Default Value: Port 1= Bit Description Size: 16 bits
Port 2= Bit Description
Port 3= Bit Description
Port 4= Bit Description
Port 5= Bit Description
Port 6= Bit Description
Port 7= Bit Description
Port 8= Bit Description
13.1.3 PCICMD—PCI Command Register (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
Bit Description
15:0 Device ID — RO. This is a 16-bit value assigned to Intel® Xeon® Processor D-1500 Product Family
’s PCI Express controller.
Bit Description
15:11 Reserved
10 Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot-Plug and power
management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power
management and MSI is not enabled.
1 = Internal INTx# messages will not be generated.
This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and
Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set.
9 Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base Specification.
8 SERR# Enable (SEE) — R/W.
0 = Disable.
1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.
7 Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification.
6 Parity Error Response (PER) — R/W.
0 = Disable.
1 = Indicates that the device is capable of reporting parity errors as a master on the backbone.
5 VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification.
4 Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base Specification.
3 Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification.