Datasheet

PCI Express* Configuration Registers
480 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
4Ah–4Bh DSTS Device Status 0010h R/WC, RO
4Ch–4Fh LCAP Link Capabilities See bit
description
RO, R/WO
50h–51h LCTL Link Control 0000h R/W, RO
52h–53h LSTS Link Status See bit
description
RO
54h–57h SLCAP Slot Capabilities Register 00060060h R/WO, RO
58h–59h SLCTL Slot Control 0000h R/W, RO
5Ah–5Bh SLSTS Slot Status 0000h R/WC, RO
5Ch–5Dh RCTL Root Control 0000h R/W
60h–63h RSTS Root Status 00000000h R/WC, RO
64h–67h DCAP2 Device Capabilities 2 Register 00080816h R/WO,RO
68h–69h DCTL2 Device Control 2 Register 0000h R/W, RO
70h–71h LCTL2 Link Control 2 Register 0002h R/W
72h–73h LSTS2 Link Status 2 Register 0000h RO
80h–81h MID Message Signaled Interrupt Identifiers 9005h RO
82h–83h MC Message Signaled Interrupt Message Control 0000h R/W, RO
84h–87h MA Message Signaled Interrupt Message
Address
00000000h R/W
88h–89h MD Message Signaled Interrupt Message Data 0000h R/W
90h–91h SVCAP Subsystem Vendor Capability A00Dh R/WO,RO
94h–97h SVID Subsystem Vendor Identification 00000000h R/WO
A0h–A1h PMCAP Power Management Capability 0001h RO
A2h–A3h PMC PCI Power Management Capability C803h RO
A4h–A7h PMCS PCI Power Management Control and Status 00000000h R/W, RO
D4h–D7h MPC2 Miscellaneous Port Configuration 2 00000800h R/W, RO
D8h–dBh MPC Miscellaneous Port Configuration 09110000h R/W, RO, R/
WO
DCh–DFh SMSCS SMI/SCI Status Register 00000000h R/WC
E1h RPDCGEN Rort Port Dynamic Clock Gating Enable 00h R/W
ECh–EFh PECR3 PCI Express Configuration Register 3 00000000h R/W
104h–107h UES Uncorrectable Error Status See bit
description
R/WC, RO
108h–10Bh UEM Uncorrectable Error Mask 00000000h R/WO, RO
10Ch–10Fh UEV Uncorrectable Error Severity 00060011h RO
110h–113h CES Correctable Error Status 00000000h R/WC
114h–117h CEM Correctable Error Mask 00002000h R/WO
118h–11Bh AECC Advanced Error Capabilities and Control 00000000h RO
130h–133h RES Root Error Status 00000000h R/WC, RO
320h–323h PECR2 PCI Express Configuration Register 2 0004B05Bh R/W
324h–327h PEETM PCI Express Extended Test Mode Register See bit
description
RO
330h–333h PEC1 PCI Express Configuration Register 1 28000016h RO, R/W
Table 13-1. PCI Express* Configuration Registers Address Map (PCI Express*—D28:F0/
F1/F2/F3/F4/F5/F6/F7) (Sheet 2 of 2)
Offset Mnemonic Register Name
Function 0–7
Default
Attribute