Datasheet

SMBus Controller Registers (D31:F3)
Intel® Xeon® Processor D-1500 Product Family 477
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
All bits in this register are implemented in the 64 kHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
12.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 11h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
12.2.17 NOTIFY_DADDR—Notify Device Address Register (SMBus—
D31:F3)
Register Offset: SMB_BASE + 14h Attribute: RO
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
7:1 Reserved
0 HOST_NOTIFY_STS — R/WC. Intel® Xeon® Processor D-1500 Product Family sets this bit to a 1
when it has completely received a successful Host Notify Command on the SMBus pins. Software
reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host
Notify Command. Software clears this bit after reading any information needed from the Notify
address and data registers by writing a 1 to this bit. Intel® Xeon® Processor D-1500 Product Family
will allow the Notify Address and Data registers to be over-written once this bit has been cleared.
When this bit is 1, Intel® Xeon® Processor D-1500 Product Family will NACK the first byte (host
address) of any new “Host Notify” commands on the SMBus pins. Writing a 0 to this bit has no effect.
Bit Description
7:2 Reserved
2 SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT#
source. This bit is logically inverted and ANDed with the SMBALERT_STS bit (offset SMB_BASE
+ 00h, bit 5). The resulting signal is distributed to the SMI# and/or interrupt generation logic.
This bit does not effect the wake logic.
1 HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a Host Notify
command as a wake event. When enabled this event is “OR’d" in with the other SMBus wake events
and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register.
0 = Disable
1 = Enable
0 HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation of interrupt or
SMI# when HOST_NOTIFY_STS (offset SMB_BASE + 10h, bit 0) is 1. This enable does not affect the
setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB# or SMI# is
generated, depending on the value of the SMB_SMI_EN bit (D31:F3:40h, bit 1). If the
HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be
generated. The interrupt (or SMI#) is logically generated by AND’ing the STS and INTREN bits.
0 = Disable
1 = Enable
Bit Description
7:1 DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during the Host
Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when
the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set to 1.
0Reserved