Datasheet
SMBus Controller Registers (D31:F3)
476 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register (SMBus—
D31:F3)
Register Offset: SMB_BASE + 0Eh Attribute: R/W, RO
Default Value: See Description Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
This register is only applicable in the TCO compatible mode.
12.2.14 SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—
D31:F3)
Register Offset: SMB_BASE + 0Fh Attribute: R/W, RO
Default Value: See Description Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
12.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 10h Attribute: R/WC
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
7:3 Reserved
2 SMLINK_CLK_CTL — R/W.
0 = Intel® Xeon® Processor D-1500 Product Family will drive the SMLink0 pin low, independent of
what the other SMLink logic would otherwise indicate for the SMLink0 pin.
1 = The SMLink0 pin is not overdriven low. The other SMLink logic controls the state of the pin.
(Default)
1 SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLink1 pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
0 SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLink0 pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
Bit Description
7:3 Reserved
2 SMBCLK_CTL — R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of the pin.
0 = Intel® Xeon® Processor D-1500 Product Family drives the SMBCLK pin low, independent of
what the other SMB logic would otherwise indicate for the SMBCLK pin. (Default)
1 SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMBDATA pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
0 SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMBCLK pin. This allows software to read the current
state of the pin.
0 = Low
1 = High