Datasheet

SMBus Controller Registers (D31:F3)
Intel® Xeon® Processor D-1500 Product Family 475
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Ah–0Bh Attribute: RO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Resume
This register contains the 16-bit data value written by the external SMBus master. The
processor can then read the value from this register. This register is reset by RSMRST#,
but not PLTRST#.
12.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Ch Attribute: R/WC, RO
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Resume
12.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Dh Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Resume
Bit Description
15:8 Data Message Byte 1 (DATA_MSG1) — RO. See Section 3.20.7 for a discussion of this field.
7:0 Data Message Byte 0 (DATA_MSG0) — RO. See Section 3.20.7 for a discussion of this field.
Bit Description
7:2 Reserved
1 SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible mode versus
Advanced TCO mode.
0 = Intel® Xeon® Processor D-1500 Product Family is in the compatible TCO mode.
1 = Intel® Xeon® Processor D-1500 Product Family is in the advanced TCO mode.
0 CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a CRC error. When this bit is set, the DERR bit of
the host status register will also be set. This bit will be set by the controller if a software abort
occurs in the middle of the CRC portion of the cycle or an abort happens after Intel® Xeon®
Processor D-1500 Product Family has received the final data bit transmitted by an external
slave.
Bit Description
7:2 Reserved
1 Enable 32-Byte Buffer (E32B) — R/W.
0 = Disable.
1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to
a single register. This enables the block commands to transfer or receive up to 32-bytes before
Intel® Xeon® Processor D-1500 Product Family generates an interrupt.
0 Automatically Append CRC (AAC) — R/W.
0 = Intel® Xeon® Processor D-1500 Product Family will Not automatically append the CRC.
1 = Intel® Xeon® Processor D-1500 Product Family will automatically append the CRC. This bit
must not be changed during SMBus transactions or undetermined behavior will result. It should
be programmed only once during the lifetime of the function.