Datasheet

SMBus Controller Registers (D31:F3)
Intel® Xeon® Processor D-1500 Product Family 473
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.2.3 HST_CMD—Host Command Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 03h Attribute: R/W
Default Value: 00h Size: 8 bits
12.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBus—
D31:F3)
Register Offset: SMB_BASE + 04h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is transmitted by the host controller in the slave address field of the
SMBus protocol.
12.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 05h Attribute: R/W
Default Value: 00h Size: 8 bits
12.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 06h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0 This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol
during the execution of any command.
Bit Description
7:1 Address — R/W. This field provides a 7-bit address of the targeted slave.
0 RW — R/W. Direction of the host transfer.
0 = Write
1 = Read
Note: Writes to SMBus addresses 50h - 57h are disabled depending on the setting of bit 4 in
HOSTC register (D31:F3:Offset 40h).
Bit Description
7:0 Data0/Count — R/W. This field contains the 8-bit data sent in the DATA0 field of the SMBus
protocol. For block write commands, this register reflects the number of bytes to transfer. This
register should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count
above 32 will result in unpredictable behavior. The host controller does not check or log invalid block
counts.
Bit Description
7:0 Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus protocol during the
execution of any command.