Datasheet

SMBus Controller Registers (D31:F3)
472 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6 START — WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset
00h) can be used to identify when Intel® Xeon® Processor D-1500 Product Family has finished
the command.
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers
should be setup prior to writing a 1 to this bit position.
5 LAST_BYTE — WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the
block. This causes Intel® Xeon® Processor D-1500 Product Family to send a NACK (instead of
an ACK) after receiving the last byte.
Note: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h, bit 1) is set,
the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is set, the LAST_BYTE bit
cannot be cleared. This prevents Intel® Xeon® Processor D-1500 Product Family from
running some of the SMBus commands (Block Read/Write, I
2
C Read, Block I
2
C Write).
4:2 SMB_CMD — R/W. The bit encoding below indicates which command Intel® Xeon® Processor D-
1500 Product Family is to perform. If enabled, Intel® Xeon® Processor D-1500 Product Family will
generate an interrupt or SMI# when the command has completed If the value is for a non-supported
or reserved command, Intel® Xeon® Processor D-1500 Product Family will set the device error
(DEV_ERR) status bit (offset SMB_BASE + 00h, bit 2) and generate an interrupt when the START bit
is set. Intel® Xeon® Processor D-1500 Product Family will perform no command, and will not
operate until DEV_ERR is cleared.
000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave
address register.
001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the
slave address register determines if this is a read or write command.
010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers.
Bit 0 of the slave address register determines if this is a read or write command. If it is a read, the
DATA0 register will contain the read data.
011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1
registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a
read, after the command completes, the DATA0 and DATA1 registers will contain the read data.
100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1
registers. Bit 0 of the slave address register determines if this is a read or write command. After the
command completes, the DATA0 and DATA1 registers will contain the read data.
101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the
Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how
many bytes of data will be transferred. For block reads, the count is received and stored in the
DATA0 register. Bit 0 of the slave address register selects if this is a read or write command. For
writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the
SRAM array. For reads, the data is stored in the Block Data Byte register.
110 = I
2
C Read: This command uses the transmit slave address, command, DATA0, DATA1
registers, and the Block Data Byte register. The read data is stored in the Block Data Byte register.
Intel® Xeon® Processor D-1500 Product Family continues reading data until the NAK is received.
111 = Block Process: This command uses the transmit slave address, command, DATA0 and the
Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how
many bytes of data will be transferred. For block read, the count is received and stored in the DATA0
register. Bit 0 of the slave address register always indicate a write command. For writes, data is
retrieved from the first m (where m is equal to the specified count) addresses of the SRAM array. For
reads, the data is stored in the Block Data Byte register.
Note: E32B bit in the Auxiliary Control register must be set for this command to work.
1 KILL — R/W.
0 = Normal SMBus host controller functionality.
1 = Kills the current host transaction taking place, sets the FAILED status bit, and asserts the
interrupt (or SMI#). This bit, once set, must be cleared by software to allow the SMBus host
controller to function normally.
0 INTREN — R/W.
0 = Disable.
1 = Enable the generation of an interrupt or SMI# upon the completion of the command.
Bit Description