Datasheet

SMBus Controller Registers (D31:F3)
Intel® Xeon® Processor D-1500 Product Family 471
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 02h Attribute: R/W, WO
Default Value: 00h Size: 8-bits
Note: A read to this register will clear the byte pointer of the 32-byte buffer.
6 INUSE_STS — R/W. This bit is used as semaphore among various independent software threads that
may need to use Intel® Xeon® Processor D-1500 Product Family ’s SMBus logic, and has no other
effect on hardware.
0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next
read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0,
and will then own the usage of the host controller.
5 SMBALERT_STS — R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by writing a 1 to
it.
1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by
software writing a 1 to the bit position or by RSMRST# going low.
If the signal is programmed as a GPIO, then this bit will never be set.
4 FAILED — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to
the KILL bit being set to terminate the host transaction.
3 BUS_ERR — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt of SMI# was a transaction collision.
2 DEV_ERR — R/WC.
0 = Software clears this bit by writing a 1 to it. Intel® Xeon® Processor D-1500 Product Family will
then de-assert the interrupt or SMI#.
1 = The source of the interrupt or SMI# was due to one of the following:
• Invalid Command Field,
• Unclaimed Cycle (host initiated),
• Host Device Time-out Error.
1 INTR — R/WC. This bit can only be set by termination of a command. INTR is not dependent on the
INTREN bit (offset SMB_BASE + 02h, bit 0) of the Host controller register (offset 02h). It is only
dependent on the termination of the command. If the INTREN bit is not set, then the INTR bit will be
set, although the interrupt will not be generated. Software can poll the INTR bit in this non-interrupt
case.
0 = Software clears this bit by writing a 1 to it. Intel® Xeon® Processor D-1500 Product Family
then de-asserts the interrupt or SMI#.
1 = The source of the interrupt or SMI# was the successful completion of its last command.
0 HOST_BUSY — R/WC.
0 = Cleared by Intel® Xeon® Processor D-1500 Product Family when the current transaction is
completed.
1 = Indicates that Intel® Xeon® Processor D-1500 Product Family is running a command from the
host interface. No SMB registers should be accessed while this bit is set, except the BLOCK DATA
BYTE Register. The BLOCK DATA BYTE Register can be accessed when this bit is set only when
the SMB_CMD bits in the Host Control Register are programmed for Block command or I
2
C Read
command. This is necessary in order to check the DONE_STS bit.
Bit Description
Bit Description
7
PEC_EN — R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase appended.
1 = Causes the host controller to perform the SMBus transaction with the Packet Error Checking
phase appended. For writes, the value of the PEC byte is transferred from the PEC Register. For
reads, the PEC byte is loaded in to the PEC Register. This bit must be written prior to the write
in which the START bit is set.