Datasheet

SMBus Controller Registers (D31:F3)
470 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.2.1 HST_STS—Host Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 00h Attribute: R/WC, RO
Default Value: 00h Size: 8-bits
All status bits are set by hardware and cleared by the software writing a one to the
particular bit position. Writing a 0 to any bit position has no effect.
Table 12-2. SMBus I/O and Memory Mapped I/O Register Address Map
SMB_BASE +
Offset
Mnemonic Register Name Default Attribute
00h HST_STS Host Status 00h R/WC, RO
02h HST_CNT Host Control 00h R/W, WO
03h HST_CMD Host Command 00h R/W
04h XMIT_SLVA Transmit Slave Address 00h R/W
05h HST_D0 Host Data 0 00h R/W
06h HST_D1 Host Data 1 00h R/W
07h HOST_BLOCK_dB Host Block Data Byte 00h R/W
08h PEC Packet Error Check 00h R/W
09h RCV_SLVA Receive Slave Address 44h R/W
0Ah–0Bh SLV_DATA Receive Slave Data 0000h RO
0Ch AUX_STS Auxiliary Status 00h R/WC, RO
0Dh AUX_CTL Auxiliary Control 00h R/W
0Eh SMLINK_PIN_CTL SMLink Pin Control (TCO Compatible
Mode)
See register
description
R/W, RO
0Fh SMBus_PIN_CTL SMBus Pin Control See register
description
R/W, RO
10h SLV_STS Slave Status 00h R/WC
11h SLV_CMD Slave Command 00h R/W
14h NOTIFY_DADDR Notify Device Address 00h RO
16h NOTIFY_DLOW Notify Data Low Byte 00h RO
17h NOTIFY_DHIGH Notify Data High Byte 00h RO
Bit Description
7 Byte Done Status (DS) — R/WC.
0 = Software can clear this by writing a 1 to it.
1 = Host controller received a byte (for Block Read commands) or if it has completed transmission of
a byte (for Block Write commands) when the 32-byte buffer is not being used. This bit will be
set, even on the last byte of the transfer. This bit is not set when transmission is due to the LAN
interface heartbeat.
This bit has no meaning for block transfers when the 32-byte buffer is enabled.
Note: When the last byte of a block message is received, the host controller will set this bit.
However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt
handler clears the DS bit, the message is considered complete, and the host controller will
then set the INTR bit (and generate another interrupt). Thus, for a block message of n bytes,
Intel® Xeon® Processor D-1500 Product Family will generate n+1 interrupts. The interrupt
handler needs to be implemented to handle these cases. When not using the 32 Byte Buffer,
hardware will drive the SMBCLK signal low when the DS bit is set until SW clears the bit. This
includes the last byte of a transfer. Software must clear the DS bit before it can clear the
BUSY bit.