Datasheet

SMBus Controller Registers (D31:F3)
Intel® Xeon® Processor D-1500 Product Family 469
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3)
Address Offset: 3Ch Attributes: R/W
Default Value: 00h Size: 8 bits
12.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3)
Address Offset: 3Dh Attributes: RO
Default Value: See description Size: 8 bits
12.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3)
Address Offset: 40h Attribute: R/W, R/WO
Default Value: 00h Size: 8 bits
12.2 SMBus I/O and Memory Mapped I/O Registers
The SMBus registers (see Ta ble 12- 2 ) can be accessed through I/O BAR or Memory BAR
registers in PCI configuration space. The offsets are the same for both I/O and Memory
Mapped I/O registers.
Bit Description
7:0 Interrupt Line (INT_LN) — R/W. This data is not used by Intel® Xeon® Processor D-1500 Product
Family . It is to communicate to software the interrupt line that the interrupt pin is connected to
PIRQB#.
Bit Description
7:0 Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset configuration
space.
Bit Description
7:5 Reserved
4 SPD Write Disable — R/WO.
0 = SPD write enabled.
1 = SPD write disabled. Writes to SMBus addresses 50h - 57h are disabled.
Note: This bit is R/WO and will be reset on PLTRST# assertion. This bit should be set by BIOS to
‘1’. SW can only program this bit when both the START bit (SMB_BASE + 02h, bit 6) and
Host Busy bit (SMB_BASE + 00h, bit 0) are ‘0’; otherwise the write may result in undefined
behavior.
3 Soft SMBus Reset (SSRESET) — R/W.
0 = The HW will reset this bit to 0 when SMBus reset operation is completed.
1 = The SMBus state machine and logic in Intel® Xeon® Processor D-1500 Product Family is reset.
2 I
2
C_EN — R/W.
0 = SMBus behavior.
1 = Intel® Xeon® Processor D-1500 Product Family is enabled to communicate with I
2
C devices.
This will change the formatting of some commands.
1 SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to
Section 3.20.4 (Interrupts / SMI#).
This bit needs to be set for SMBALERT# to be enabled.
0 SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit
(offset SMB_BASE + 02h, bit 0) needs to be enabled for the SMB Host controller to interrupt or
SMI#. The SMB Host controller will not respond to any new requests until all interrupt requests
have been cleared.