Datasheet
SMBus Controller Registers (D31:F3)
468 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1
Register (SMBus—D31:F3)
Address Offset: 14h–17h Attributes: R/W
Default Value: 00000000h Size: 32 bits
12.1.11 SMB_BASE—SMBus Base Address Register (SMBus—
D31:F3)
Address Offset: 20–23h Attribute: R/W, RO
Default Value: 00000001h Size: 32-bits
12.1.12 SVID—Subsystem Vendor Identification Register (SMBus—
D31:F2/F4)
Address Offset: 2Ch–2Dh Attribute: RO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
12.1.13 SID—Subsystem Identification Register (SMBus—D31:F2/
F4)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
31:0 Base Address — R/W. Provides bits 63:32 system memory base address for Intel® Xeon®
Processor D-1500 Product Family SMB logic.
Bit Description
31:16 Reserved — RO
15:5 Base Address — R/W. This field provides the 32-byte system I/O base address for Intel® Xeon®
Processor D-1500 Product Family ’s SMB logic.
4:1 Reserved — RO
0 IO Space Indicator — RO. Hardwired to 1 indicating that the SMB logic is I/O mapped.
Bit Description
15:0 Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the Subsystem ID
(SID) register, enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS into the IDE
SVID register.
Note: Software can write to this register only once per core well reset. Writes should be done as a
single 16-bit cycle.
Bit Description
15:0 Subsystem ID (SID) — R/WO. The SID register, in combination with the SVID register, enables the
operating system (OS) to distinguish subsystems from each other. The value returned by reads to this
register is the same as that which was written by BIOS into the IDE SID register.
Note: Software can write to this register only once per core well reset. Writes should be done as a
single 16-bit cycle.