Datasheet

SMBus Controller Registers (D31:F3)
Intel® Xeon® Processor D-1500 Product Family 467
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.1.5 RID—Revision Identification Register (SMBus—D31:F3)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
12.1.6 PI—Programming Interface Register (SMBus—D31:F3)
Offset Address: 09h Attribute: RO
Default Value: 00h Size: 8 bits
12.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)
Address Offset: 0Ah Attributes: RO
Default Value: 05h Size: 8 bits
12.1.8 BCC—Base Class Code Register (SMBus—D31:F3)
Address Offset: 0Bh Attributes: RO
Default Value: 0Ch Size: 8 bits
12.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0
Register (SMBus—D31:F3)
Address Offset: 10–13h Attributes: R/W, RO
Default Value: 00000004h Size: 32 bits
3 Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent
from the state of the Interrupt Enable bit in the PCI Command register.
2:0 Reserved
Bit Description
7:0 Revision ID — RO. This field indicates the device specific revision identifier.
Bit Description
7:0 Reserved
Bit Description
7:0 Sub Class Code (SCC) — RO.
05h = SMBus serial controller
Bit Description
7:0 Base Class Code (BCC) — RO.
0Ch = Serial controller.
Bit Description
31:8 Base Address — R/W. Provides the 32 byte system memory base address for Intel® Xeon®
Processor D-1500 Product Family SMB logic.
7:4 Reserved
3 Prefetchable (PREF) — RO. Hardwired to 0. Indicates that SMBMBAR is not pre-fetchable.
2:1 Address Range (ADDRNG) — RO. Indicates that this SMBMBAR can be located anywhere in 64 bit
address space. Hardwired to 10b.
0 Memory Space Indicator — RO. This read-only bit always is 0, indicating that the SMB logic is
Memory mapped.