Datasheet

SMBus Controller Registers (D31:F3)
466 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12.1.3 PCICMD—PCI Command Register (SMBus—D31:F3)
Address: 04h–05h Attributes: RO, R/W
Default Value: 0000h Size: 16 bits
12.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)
Address: 06h–07h Attributes: RO
Default Value: 0280h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
15:11 Reserved
10 Interrupt Disable — R/W.
0 = Enable
1 = Disables SMBus to assert its PIRQB# signal.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8 SERR# Enable (SERR_EN) — R/W.
0 = Enables SERR# generation.
1 = Disables SERR# generation.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6 Parity Error Response (PER) — R/W.
0 = Disable
1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — RO. Hardwired to 0.
1 Memory Space Enable (MSE) — R/W.
0 = Disables memory mapped config space.
1 = Enables memory mapped config space.
0 I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SMBus I/O space registers as defined by the Base Address Register.
Bit Description
15 Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Parity error detected.
14 Signaled System Error (SSE) — R/WC.
0 = No system error detected.
1 = System error detected.
13 Received Master Abort (RMA) — RO. Hardwired to 0.
12 Received Target Abort (RTA) — RO. Hardwired to 0.
11 Signaled Target Abort (STA) — RO. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL# assertion
for positive decode.
01 = Medium timing.
8 Data Parity Error Detected (DPED) — RO. Hardwired to 0.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
4 Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list structures in
this function