Datasheet

xHCI Controller Registers (D20:F0)
462 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.3.8 ERDPH—Event Ring Dequeue Pointer High X Register
Offset: 1: Runtime Base + 3Ch–3Fh
2: Runtime Base + 5Ch–5Fh
3: Runtime Base + 7Ch–7Fh
4: Runtime Base + 9Ch–9Fh
5: Runtime Base + BCh–BFh
6: Runtime Base + DCh–DFh
7: Runtime Base + FCh–FFh
8: Runtime Base + 11Ch–11Fh
Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERDPH registers.
11.3.4 Doorbell Registers
Door Bell registers are an array of 64 registers, with 0 to 32 being used by the xHC and
the remainder being reserved. One 32-bit Doorbell Register is defined in the array for
each Device Slot. System software utilizes the Doorbell Register to notify the xHC that
it has Device Slot related work for the xHC to perform.
These registers are pointed to by the Doorbell Offset Register (dBOFF) in the xHC
Capability register space. The Doorbell Array base address shall be DWord aligned and
is calculated by adding the value in the dBOFF register (MEM_BASE+14h-17h) to
“Base” (the base address of the xHCI Capability register address space).
All registers are 32 bits in length. Software should read and write these registers using
only DWord accesses.
11.3.4.1 DOORBELL—Doorbell X Register
Offset: Doorbell 1: dBOFF + 00h-03h
Doorbell 2: dBOFF + 04h-07h
....
Doorbell 32: dBOFF + 7Ch-7Fh
Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well Core
Note: There are 32 contiguous DOORBELL registers.
Note: Reading this register will always show 00000000h.
Bit Description
31:0 Event Ring Dequeue Pointer — R/W. This field defines the low order bits of the 64- bit address of
the current Event Ring Dequeue Pointer.