Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 461
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.3.6 ERSTBAH—Event Ring Segment Table Base Address High X Register
Offset: 1: Runtime Base + 34h–37h
2: Runtime Base + 54h–57h
3: Runtime Base + 74h–77h
4: Runtime Base + 94h–97h
5: Runtime Base + B4h–B7h
6: Runtime Base + D4h–D7h
7: Runtime Base + F4h–F7h
8: 1Runtime Base + 14h–117h
Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERSTBAH registers.
11.3.3.7 ERDPL—Event Ring Dequeue Pointer Low X Register
Offset: 1: Runtime Base + 38h–3Bh
2: Runtime Base + 58h–5Bh
3: Runtime Base + 78h–7Bh
4: Runtime Base + 98h–9Bh
5: Runtime Base + B8h–BBh
6: Runtime Base + D8h–dBh
7: Runtime Base + F8h–FBh
8: Runtime Base + 118h–11Bh
Attribute: R/W, R/WC
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERDPL registers.
Bit Description
31:0 Event Ring Segment Table Base Address Register (ERSTBA_HI) — R/W. This field defines the
low order bits of the start address of the Event Ring Segment Table.
This field shall not be modified if HCHalted (HCH) = 0.
Bit Description
31:4 Event Ring Dequeue Pointer — R/W. This field defines the low order bits of the 64- bit address of
the current Event Ring Dequeue Pointer.
3 Event Handler Busy (EHB) — R/WC. This flag shall be set to ‘1’ when the IP bit is set to ‘1’ and
cleared to ‘0’ by software when the Dequeue Pointer register is written.
2:0 Dequeue ERST Segment Index (DESI) — R/W. This field may be used by the xHC to accelerate
checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of
the ERST entry which defines the Event Ring segment that Event Ring Dequeue Pointer resides in.