Datasheet

xHCI Controller Registers (D20:F0)
460 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.3.4 ERSTSZ—Event Ring Segment Table Size X Register
Offset: 1: Runtime Base + 28h–2Bh
2: Runtime Base + 48h–4Bh
3: Runtime Base + 68h–6Bh
4: Runtime Base + 88h–8Bh
5: Runtime Base + A8h–ABh
6: Runtime Base + C8h–CBh
7: Runtime Base + E8h–EBh
8: Runtime Base + 108h–10Bh
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERSTSZ registers.
11.3.3.5 ERSTBAL—Event Ring Segment Table Base Address Low X Register
Offset: 1: Runtime Base + 30h–33h
2: Runtime Base + 50h–53h
3: Runtime Base + 70h–73h
4: Runtime Base + 90h–93h
5: Runtime Base + B0h–B3h
6: Runtime Base + D0h–D3h
7: Runtime Base + F0h–F3h
8: Runtime Base + 110h–113h
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERSTBAL registers.
Bit Description
31:16 Interrupt Moderation Counter (IMODC) — R/W. Down counter. Loaded with Interval Moderation
value (value of bits 15:0) whenever the IP bit is cleared to 0b, counts down to ‘0’, and stops. The
associated interrupt shall be signaled whenever this counter is ‘0’, the Event Ring is not empty, the
IE and IP bits = 1, and EHB = 0.
This counter may be directly written by software at any time to alter the interrupt rate.
15:0 Interrupt Moderation Interval (IMODI) — R/W. Minimum inter-interrupt interval. The interval is
specified in 250ns increments. A value of ‘0’ disables interrupt throttling logic and interrupts shall be
generated immediately if IP = 0, EHB = 0, and the Event Ring is not empty.
Bit Description
31:16 Reserved.
15:0 Event Ring Segment Table Size — R/W. This field identifies the number of valid Event Ring
Segment Table entries in the Event Ring Segment Table pointed to by the Event Ring Segment Table
Base Address register.
Bit Description
31:6 Event Ring Segment Table Base Address Register (ERSTBA_LO) — R/W. This field defines the
low order bits of the start address of the Event Ring Segment Table.
This field shall not be modified if HCHalted (HCH) = 0.
5:0 Reserved.