Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 459
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.3.1 MFINDEX—Microframe Index Register
Offset: Runtime Base + 00h-03h Attribute: RO,
Default Value: 00000000h Size: 32 bits
11.3.3.2 IMAN—Interrupter X Management Register
Offset: Interrupter 1: Runtime Base + 20h–23h
Interrupter 2: Runtime Base + 40h–43h
Interrupter 3: Runtime Base + 60h–63h
Interrupter 4: Runtime Base + 80h–83h
Interrupter 5: Runtime Base + A0h–A3h
Interrupter 6: Runtime Base + C0h–C3h
Interrupter 7: Runtime Base + E0h–E3h
Interrupter 8: Runtime Base + 100h–103h
Attribute: RO, R/W, R/WC
Default Value: 00000000h Size: 32 bits
Note: The xHC implements up to 8 Interrupters. There are 8 IMAN registers, one for each
Interrupter.
11.3.3.3 IMOD—Interrupter X Moderation Register
Offset: Interrupter 1: Runtime Base + 24h–27h
Interrupter 2: Runtime Base + 44h–47h
Interrupter 3: Runtime Base + 64h–67h
Interrupter 4: Runtime Base + 84h–87h
Interrupter 5: Runtime Base + A4h–A7h
Interrupter 6: Runtime Base + C4h–C7h
Interrupter 7: Runtime Base + E4h–E7h
Interrupter 8: Runtime Base + 104h–107h
Attribute: R/W
Default Value: 00000FA0h Size: 32 bits
Note: The xHC implements up to 8 Interrupters. There are 8 IMOD registers, one for each
Interrupter.
Bit Description
31:14 Reserved.
13:0 Microframe Index — RO. The value in this register increments at the end of each microframe (such
as 125 us.). Bits 13:3 may be used to determine the current 1ms. Frame Index.
Bit Description
31:2 Reserved.
1 Interrupt Enable (IE) — RO. This flag specifies whether the Interrupter is capable of generating an
interrupt.
0 = The Interrupter is prohibited from generating interrupts.
1 = When this bit and the IP bit are set (1b), the Interrupter shall generate an interrupt when the
Interrupter Moderation Counter reaches ‘0’.
0 Interrupt Pending (IP) — R/WC.
0 = No interrupt is pending for the Interrupter.
1 = An interrupt is pending for this Interrupter.
This bit is set to 1b when IE = 1, the IMODI Interrupt Moderation Counter field = 0b, the Event Ring
associated with the Interrupter is not empty (or for the Primary Interrupter when the HCE flag is set
to 1b), and EHB = 0.
If MSI interrupts are enabled, this flag shall be cleared automatically when the PCI DWord write
generated by the Interrupt assertion is complete. If PCI Pin Interrupts are enabled, this flag shall be
cleared by software.