Datasheet

xHCI Controller Registers (D20:F0)
458 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.14 PORTLIX— USB 3.0 Port X Link Info Register
Offset: There are 6 USB3 PORTLIX registers at offsets:
578h, 588h, 598h, 5A8h, 5B8h, 5C8h
Attribute: RO
Default Value: 00000000h Size: 32 bits
11.3.3 Host Controller Runtime Registers
This section defines the xHC runtime registers. The base address of this register space
is referred to as Runtime Base. The Runtime Base shall be 32-byte aligned and is
calculated by adding the value Runtime Register Space Offset register
(MEM_BASE+18h:bits 31:2) to the Capability Base address. All Runtime registers are
multiples of 32 bits in length.
7:0 U1 Timeout — R/W. Timeout value for U1 inactivity timer.
If equal to FFh, the port is disabled from initiating U1 entry. This field shall be cleared to 0 by the
assertion of PR to 1. Refer to Section 4 of the xHCI Specification for more information on U1 Timeout
operation. The following are permissible values:
Bit Description
Value Description
00h Zero (default)
01h 1 μs
02h 2 μs
...
7Fh 127 μs
80h-FEh Reserved
FFh Infinite
Bit Description
31:16 Reserved.
15:0 Link Error Count - RO.
Table 11-4. Enhanced Host Controller Operational Register Address Map
Runtime
Base + Offset
Power
Well
Mnemonic Register Name Default
Special
Notes
Type
00h–03h Core MFINDEX Microframe Index 00000000h RO
20h–23h Core IMAN Interrupter X
Management
00000000h RO, R/W,
R/WC
24h–27h Core IMOD Interrupter X Moderation 00000FA0h R/W
28h–2Bh Core ERSTSZ Event Ring Segment
Tab l e S i z e X
00000000h R/W, RO
30h–33h Core ERSTBAL Event Ring Segment
Table Base Address Low
X
00000000h R/W, RO
34h–37h Core ERSTBAH Event Ring Segment
Table Base Address High
X
00000000h R/W
38h–3Bh Core ERDPL Event Ring Dequeue
Pointer Low X
00000000h R/W, R/WC
3Ch–3Fh Core ERDPH Event Ring Dequeue
Pointer High X
00000000h R/W