Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 457
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.13 PORTPMSCN—Port N Power Management Status and Control USB3
Register
Offset: There are 6 USB3 PORTPMSCN registers at offsets:
574h, 584h, 594h, 5A4h, 5B4h, 5C4h
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
4 Port Reset (PR) — R/W. When software writes a 1 to this bit (from a 0), the bus reset sequence as
defined in the USB Specification, Revision 2.0 is started. Software writes a 0 to this bit to terminate
the bus reset sequence. Software must keep this bit at a 1 long enough to ensure the reset sequence
completes as specified in the USB Specification, Revision 2.0. USB 3.0 ports shall execute the Hot
Reset sequence as defined in the USB 3.0 Specification. PR remains set until reset signaling is
completed by the root hub.
1 = Port is in Reset.
0 = Port is not in Reset.
Note: This bit is in the Suspend Well.
3 Overcurrent Active (OCA)— RO.
0 = This port does not have an overcurrent condition. (Default)
1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0
when the over current condition is removed. Intel® Xeon® Processor D-1500 Product Family
automatically disables the port when the overcurrent active bit is 1.
Note: This bit is in the Suspend Well.
2 Reserved.
1 Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a part of the
reset and enable. Software cannot enable a port by writing a 1 to this bit. Ports can be disabled by
either a fault condition (disconnect event or other fault condition) or by host software. The bit status
does not change until the port state actually changes. There may be a delay in disabling or enabling
a port due to other host controller and bus events.
0 = Disable
1 = Enable (Default)
Note: This bit is in the Suspend Well.
0 Current Connect Status — RO. This value reflects the current state of the port, and may not
correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
0 = No device is present. (Default)
1 = Device is present on port.
Note: This bit is in the Suspend Well.
Bit Description
Bit Description
31:17 Reserved.
16 Force Link PM Accept (FLA) — R/W. When this bit is set to ‘1’, the port shall generate a Set Link
Function LMP with the Force_LinkPM_Accept bit asserted.
This bit shall be cleared to 0b by the assertion of PR to 1 or when CCS = transitions from 0 to 1.
Writes to this flag have no affect if PP = 0b.
The Set Link Function LMP is sent by the xHC to the device connected on this port when this bit
transitions from 0’ to 1. Refer to Sections 8.4.1, 10.4.2.2 and 10.4.2.9 of the USB 3.0 Specification
for more details.
15:8 U2 Timeout — R/W. Timeout value for U2 inactivity timer.
If equal to FFh, the port is disabled from initiating U2 entry. This field shall be cleared to 0 by the
assertion of PR to 1. Refer to Section 4 of the xHCI Specification for more information on U2 Timeout
operation. The following are permissible values:
Value Description
00h Zero (default)
01h 256 μs
02h 512 μs
...
FEh 65.024 ms
FFh Infinite