Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 455
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
21 Port Reset Change (PRC) — R/WC. This flag is set to ‘1’ due a '1' to '0' transition of Port Reset
(PR); such as when any reset processing on this port is complete.
0 = No change
1 = Reset Complete
Notes:
1. This bit shall not be set to 1b if the reset processing was forced to terminate due to software
clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
20 Over-current Change (OCC) — R/WC. The functionality of this bit is not dependent upon the port
owner. Software clears this bit by writing a 1 to it.
0 = No change. (Default)
1 = There is a change to Overcurrent Active.
Note: This bit is in the Suspend Well.
19 Warm Port Reset Change (WRC) — R/WC. This bit is set when Warm Reset processing on this
port completes.
0 = No change. (Default)
1 = Warm reset complete
Notes:
1. This bit shall not be set to 1b if the reset processing was forced to terminate due to software
clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0 capable-only
ports.
4. This bit is in the Suspend Well.
18 Port Enabled/Disabled Change (PEC) — R/WC.
0 = No change. (Default)
1 = There is a change to PED bit.
Notes:
1. This bit shall not be set if the PED transition was due to software setting the PP bit to 0.
2. Software shall clear this bit by writing a 1 to it.
3. For a USB 2.0-only port, this bit shall be set to 1 only when the port is disabled due to the
appropriate conditions existing at the EOF2 point. (See Chapter 11 of the USB Specification for
the definition of a port error).
4. For a USB 3.0 port, this bit shall be set to ‘1’ if an enabled port transitions to a Disabled state
(that is, a ‘1’ to ‘0’ transition of PED). Refer to Section 4 of the xHCI Specification for more
information.
5. This bit is in the Suspend Well.
17 Connect Status Change (CSC) — R/WC. This flag indicates a change has occurred in the port’s
Current Connect Status (CCS) or Cold Attach Status (CAS) bits.
0 = No change. (Default)
1 = There is a change to the CCS or CAS bit.
The xHC sets this bit to 1b for all changes to the port device connect status, even if system software
has not cleared an existing Connect Status Change. For example, the insertion status changes twice
before system software has cleared the changed condition, root hub hardware will be “setting” an
already-set bit (that is, the bit will remain 1b).
Notes:
1. This bit shall not be set if the CCS transition was due to software setting the PP bit to 0b, or the
CAS bit transition was die to software setting the WPR bit to 1b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
16 Port Link State Write Strobe (LWS) — R/W.
0 = When 0b, write data in PLS field is ignored. (Default)
1 = When this bit is set to 1b on a write reference to this register, this flag enables writes to the PLS
field.
Reads to this bit return ‘0’.
Note: This bit is in the Suspend Well.
15:14 Reserved.
Bit Description