Datasheet

xHCI Controller Registers (D20:F0)
454 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
27 Wake on Over-current Enable (WOE) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1b enables the port to be sensitive to over-current conditions as
system wake-up events.
Note: This bit is in the Suspend Well.
26 Wake on Disconnect Enable (WDE) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device disconnects as system
wake-up events.
Note: This bit is in the Suspend Well.
25 Wake on Connect Enable (WCE) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device connects as system
wake-up events.
Note: This bit is in the Suspend Well.
24 Cold Attach Status (CAS) — RO. This bit indicates that far-end terminations were detected in the
Disconnected state and the Root Hub Port State Machine was unable to advance to the Enabled
state.
Software shall clear this bit by writing a 1b to the WPR bit or the xHC shall clear this bit if the CSS bit
transitions to 1.
Note: This bit is 0b if the PP bit is 0b or for USB 2.0 capable-only ports.
Note: This bit is in the Suspend Well.
23 Port Config Error Change (CEC) — R/WOC. This flag indicates that the port failed to configure its
link partner.
Software shall clear this bit by writing a 1 to it.
Note: This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0 capable-only
ports.
Note: This bit is in the Suspend Well.
22 Port Link State Change (PLC) — R/WC.
0 = No change
1 = Link Status Change
This flag is set to ‘1’ due to the following Port Link State (PLS) transitions:
Notes:
1. This bit shall not be set if the PLS transition was due to software setting the PP bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
Bit Description
Transition Condition
U3 -> Resume Wakeup signaling from a device
Resume -> Recovery -> U0 Device Resume complete (USB 3.0 capable ports
only)
Resume -> U0 Device Resume complete (USB 2.0 capable-only
ports)
U3 -> Recovery -> U0 Software Resume complete (USB 3.0 capable ports
only)
U3 -> U0 Software Resume complete (USB 2.0 capable-only
ports)
U2 -> U0 L1 Resume complete (USB 2.0 capable-only ports)
U0 -> U0 L1 Entry Reject (USB 2.0 capable-only ports)
U0 -> Disabled L1 Entry Error (USB 2.0 capable-only ports)
Any state -> Inactive Error (USB 3.0 capable ports only)