Datasheet
xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 453
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.12 PORTSCNUSB3—xHCI USB 3.0 Port N Status and Control Register
Offset: There are 6 USB3 PORTSC registers at offsets:
570h, 580h, 590h, 5A0h, 5B0h, 5C0h
Attribute: R/W,RO
Default Value: 000002A0h Size: 32 bits
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
•Port disabled.
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the xHCI Specification for operational requirements for how change events interact with
port suspend mode.
15:8 L1 Device Slot — R/W. System software sets this field to indicate the ID of the Device Slot
associated with the device directly attached to the Root Hub port. A value of 0 indicates there is no
device present.
Note: This bit is in the Suspend Well.
7:4 Host Initiated Resume Duration (HIRD) — R/W. System software sets this field to indicate to the
recipient device how long the xHC will drive resume if it (the xHC) initiates an exit from L1.
The HIRD value is encoded as follows: The value of 0000b is interpreted as 50 μs. Each incrementing
value up adds 75 μs to the previous value. For example, 0001b is 125 μs, 0010b is 200 μs and so on.
Based on this rule, the maximum value resume drive time is at encoding value 1111b which
represents 1.2ms. Refer to Section 4 of the USB 2.0 LPM Specification for more information.
Note: This bit is in the Suspend Well.
3 Remote Wake Enable (RWE) — R/W. The host system sets this flag to enable or disable the device
for remote wake from L1.
0 = Disable. (Default)
1 = Enable.
The value of this flag will temporarily (while in L1) override the current setting of the Remote Wake
feature set by the standard Set/ClearFeature() commands defined in Universal Serial Bus
Specification, revision 2.0, Chapter 9.
Note: This bit is in the Suspend Well.
2:0 L1 status - RO.
Note: This bit is in the Suspend Well.
Bit Description
Bit Description
31 Warm Port Reset (WPR) — R/WO. When software sets this bit to 1b, the Warm Reset sequence is
initiated and the PR bit is set to 1b. Once initiated, the PR, PRC, and WRC bits shall reflect the
progress of the Warm Reset sequence. This flag shall always return 0b when read.
Note: This bit applies only to USB 3.0 capable ports. For ports that are only USB 2.0 capable, this
bit is Reserved.
Note: This bit is in the Suspend Well.
30 Device Removable (DR) — RO. This bit indicates if this port has a removable device
attached.
0 = Device is removable.
1 = Device is non-removable.
Note: This bit is in the Core Well.
29:28 Reserved.