Datasheet
xHCI Controller Registers (D20:F0)
452 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.11 PORTPMSCNUSB2—xHCI Port N Power Management Status and
Control USB2 Register
Offset: There are 15 USB2 PORTPMSC registers at offsets:
484h, 494h, 4A4h, 4B4h, 4C4h, 4D4h, 4E4h, 4F4h,
504h, 514h, 524h, 534h, 544h, 554h, 564h
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
3 Overcurrent Active (OCA)— RO.
0 = This port does not have an overcurrent condition. (Default)
1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0
when the over current condition is removed. Intel® Xeon® Processor D-1500 Product Family
automatically disables the port when the overcurrent active bit is 1.
Note: This bit is in the Suspend Well.
2Reserved.
1 Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a part of the
reset and enable. Software cannot enable a port by writing a 1 to this bit. Ports can be disabled by
either a fault condition (disconnect event or other fault condition) or by host software. The bit status
does not change until the port state actually changes. There may be a delay in disabling or enabling
a port due to other host controller and bus events.
0 = Disable
1 = Enable (Default)
Note: This bit is in the Suspend Well.
0 Current Connect Status — RO. This value reflects the current state of the port, and may not
correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
0 = No device is present. (Default)
1 = Device is present on port.
Note: This bit is in the Suspend Well.
Bit Description
Bit Description
31:28 Port Test Control — R/W. When this field is ‘0’, the port is not operating in a test mode. (Default)
A non-zero value indicates that the port is operating in test mode and the specific test mode is
indicated by the specific value.
A non-zero Port Test Control value is only valid to a port that is in the Disabled state. If the port is
not in this state, the xHC shall respond with the Port Test Control field set to Port Test Control Error.
The encoding of the Test Mode bits for a USB 2.0 port are:
Refer to the Sections 7.1.20 and 11.24.2.13 of the USB 2.0 Specification for more information on
Tes t M o de s .
Note: This bit is in the Suspend Well.
27:17 Reserved.
16 Hardware LPM Enable (HLE) — RO.
0 = Disable.
1 = Enable. When this bit is a 1, hardware controlled LPM shall be enabled for this port. Refer to
Section 4 of the USB 2.0 LPM Specification for more information.
Note: This bit is in the Suspend Well.
Value Test Mode
0h Test mode not enabled
1h Test J_STATE
2h Test K_STATE
3h Test SE0_NAK
4h Test Packet
5h Test FORCE_ENABLE
6h-14h Reserved.
15 Port Test Control Error