Datasheet

xHCI Controller Registers (D20:F0)
450 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
18 Port Enabled/Disabled Change (PEC) — R/WC.
0 = No change. (Default)
1 = There is a change to PED bit.
Notes:
1. This bit shall not be set if the PED transition was due to software setting the PP bit to 0.
2. Software shall clear this bit by writing a 1 to it.
3. For a USB 2.0-only port, this bit shall be set to 1 only when the port is disabled due to the
appropriate conditions existing at the EOF2 point. (See Chapter 11 of the USB Specification for
the definition of a port error).
4. For a USB 3.0 port, this bit shall be set to ‘1’ if an enabled port transitions to a Disabled state
(that is, a ‘1’ to ‘0’ transition of PED). Refer to Section 4 of the xHCI Specification for more
information.
5. This bit is in the Suspend Well.
17 Connect Status Change (CSC) — R/WC. This flag indicates a change has occurred in the port’s
Current Connect Status (CCS) or Cold Attach Status (CAS) bits.
0 = No change. (Default)
1 = There is a change to the CCS or CAS bit.
The xHC sets this bit to 1b for all changes to the port device connect status, even if system software
has not cleared an existing Connect Status Change. For example, the insertion status changes twice
before system software has cleared the changed condition, root hub hardware will be “setting” an
already-set bit (that is, the bit will remain 1b).
Notes:
1. This bit shall not be set if the CCS transition was due to software setting the PP bit to 0b, or the
CAS bit transition was die to software setting the WPR bit to 1b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
16 Port Link State Write Strobe (LWS) — R/W.
0 = When 0b, write data in PLS field is ignored. (Default)
1 = When this bit is set to 1b on a write reference to this register, this flag enables writes to the PLS
field.
Reads to this bit return ‘0’.
Note: This bit is in the Suspend Well.
15:14 Reserved.
13:10 Port Speed (Port_Speed).
A device attached to this port operates at a speed defined by the following codes:
All other values reserved. Please refer to the eXtensible Host Controller Interface for Universal Serial
Bus Specification for additional details.
Note: This bit is in the Suspend Well.
9 Port Power (PP) — RO. Read-only with a value of 1. This indicates that the port does have power.
Note: This bit is in the Suspend Well.
Bit Description
Value Speed
0001b Full-speed (12 Mb/s)
0010b Low-speed (1.5 Mb/s)
0011b High-speed (480 Mb/s)