Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 449
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
23 Port Config Error Change (CEC) — R/WOC. This flag indicates that the port failed to configure its
link partner.
Software shall clear this bit by writing a 1 to it.
Note: This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0 capable-only
ports.
Note: This bit is in the Suspend Well.
22 Port Link State Change (PLC) — R/WC.
0 = No change
1 = Link Status Change
This flag is set to ‘1’ due to the following Port Link State (PLS) transitions:
Notes:
1. This bit shall not be set if the PLS transition was due to software setting the PP bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
21 Port Reset Change (PRC) — R/WC. This flag is set to ‘1’ due a '1' to '0' transition of Port Reset
(PR); such as when any reset processing on this port is complete.
0 = No change
1 = Reset Complete
Notes:
1. This bit shall not be set to 1b if the reset processing was forced to terminate due to software
clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
20 Over-current Change (OCC) — R/WC. The functionality of this bit is not dependent upon the port
owner. Software clears this bit by writing a 1 to it.
0 = No change. (Default)
1 = There is a change to Overcurrent Active.
Note: This bit is in the Suspend Well.
19 Warm Port Reset Change (WRC) — R/WC. This bit is set when Warm Reset processing on this
port completes.
0 = No change. (Default)
1 = Warm reset complete
Notes:
1. This bit shall not be set to 1b if the reset processing was forced to terminate due to software
clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0 capable-only
ports.
4. This bit is in the Suspend Well.
Bit Description
Transition Condition
U3 -> Resume Wakeup signaling from a device
Resume -> Recovery -> U0 Device Resume complete (USB 3.0 capable ports
only)
Resume -> U0 Device Resume complete (USB 2.0 capable-only
ports)
U3 -> Recovery -> U0 Software Resume complete (USB 3.0 capable ports
only)
U3 -> U0 Software Resume complete (USB 2.0 capable-only
ports)
U2 -> U0 L1 Resume complete (USB 2.0 capable-only ports)
U0 -> U0 L1 Entry Reject (USB 2.0 capable-only ports)
U0 -> Disabled L1 Entry Error (USB 2.0 capable-only ports)
Any state -> Inactive Error (USB 3.0 capable ports only)