Datasheet

xHCI Controller Registers (D20:F0)
448 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.10 PORTSCNUSB2—Port N Status and Control USB2 Register
Offset: There are 15 USB2 PORTSC registers at offsets:
480h, 490h, 4A0h, 4B0h, 4C0h, 4D0h, 4E0h, 4F0h,
500h, 510h, 520h, 530h, 540h, 550h, 560h
Attribute: R/W, R/WC, RO, R/WO, R/WOC
Default Value: 000002A0h Size: 32 bits
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
• Port disabled.
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the xHCI Specification for operational requirements for how change events interact with
port suspend mode.
Bit Description
31 Warm Port Reset (WPR) — R/WO. When software sets this bit to 1b, the Warm Reset sequence is
initiated and the PR bit is set to 1b. Once initiated, the PR, PRC, and WRC bits shall reflect the
progress of the Warm Reset sequence. This flag shall always return 0b when read.
Note: This bit applies only to USB 3.0 capable ports. For ports that are only USB 2.0 capable, this
bit is Reserved.
Note: This bit is in the Suspend Well.
30 Device Removable (DR) — RO. This bit indicates if this port has a removable device
attached.
0 = Device is removable.
1 = Device is non-removable.
Note: This bit is in the Core Well.
29:28 Reserved.
27 Wake on Over-current Enable (WOE) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1b enables the port to be sensitive to over-current conditions as
system wake-up events.
Note: This bit is in the Suspend Well.
26 Wake on Disconnect Enable (WDE) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device disconnects as system
wake-up events.
Note: This bit is in the Suspend Well.
25 Wake on Connect Enable (WCE) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device connects as system
wake-up events.
Note: This bit is in the Suspend Well.
24 Cold Attach Status (CAS) — RO. This bit indicates that far-end terminations were detected in the
Disconnected state and the Root Hub Port State Machine was unable to advance to the Enabled
state.
Software shall clear this bit by writing a 1b to the WPR bit or the xHC shall clear this bit if the CSS bit
transitions to 1.
Note: This bit is 0b if the PP bit is 0b or for USB 2.0 capable-only ports.
Note: This bit is in the Suspend Well.