Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 447
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.6 CRCRH—Command Ring Control High Register
Offset: MEM_BASE + 9Ch–9Fh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
11.3.2.7 DCBAAPL—Device Context Base Address Array Pointer Low Register
Offset: MEM_BASE + B0h–B3h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
11.3.2.8 DCBAAPH—Device Context Base Address Array Pointer High Register
Offset: MEM_BASE + B4h–B7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
11.3.2.9 CONFIG—Configure Register
Offset: MEM_BASE + B8h–BBh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 Command Ring Pointer — R/W. This field defines high order bits of the initial value of the 64-bit
Command Ring Dequeue Pointer.
Notes:
1. Writes to this field are ignored when Command Ring Running bit (CRR) = 1b.
2. If the CRCR register is written while the Command Ring is stopped (CRR = 0b), the value of this
field shall be used to fetch the first Command TRB the next time the Host Controller Doorbell
register is written with the dB Reason field set to Host Controller Command.
3. If the CRCR register is not written while the Command Ring is stopped (CRR = 0b), then the
Command Ring shall begin fetching Command TRBs at the current value of the internal xHC
Command Ring Dequeue Pointer.
4. Reading this field always returns 0b.
Bit Description
31:6 Device Context Base Address Array Pointer — R/W. This field defines low order bits of the 64-bit
base address of the Device Context Pointer Array table (a table of address pointers that reference
Device Context structures for the devices attached to the host.)
5:0 Reserved.
Bit Description
31:0 Device Context Base Address Array Pointer — R/W. This field defines high order bits of the 64-
bit base address of the Device Context Pointer Array table (a table of address pointers that reference
Device Context structures for the devices attached to the host.)
Bit Description
31:8 Reserved.
7:0 Max Device Slots Enabled (MaxSlotsEn) — R/W. This field specifies the maximum number of
enabled Device Slots. Valid values are in the range of 0h to 20h. Enabled Devices Slots are allocated
contiguously (such that a value of 16 specifies that Device Slots 1 to 16 are active.)
A value of ‘0’ disables all Device Slots. A disabled Device Slot shall not respond to Doorbell Register
references.
Note: This field shall not be modified if the xHC is running (Run/Stop (R/S) = ‘1’).