Datasheet

xHCI Controller Registers (D20:F0)
446 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.5 CRCRL—Command Ring Control Low Register
Offset: MEM_BASE + 98h–9Bh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Notes:
1. Setting the Command Stop (CS) or Command Abort (CA) flags while CRR = 1b shall generate a Command
Ring Stopped Command Completion Event.
2. Setting both the Command Stop (CS) and Command Abort (CA) flags with a single write to the CRCR
register while CRR = ‘1’ shall be interpreted as a Command Abort (CA) by the xHC.
3. The values of the internal xHC Command Ring CCS flag and Dequeue Pointer are undefined after hardware
reset, so these fields shall be initialized before setting USB_CMD Run/Stop (R/S) bit (MEM_BASE+80:bit 0)
to 1b.
Bit Description
31:6 Command Ring Pointer — R/W. This field defines low order bits of the initial value of the 64-bit
Command Ring Dequeue Pointer.
Notes:
1. Writes to this field are ignored when Command Ring Running bit (CRR) = 1b.
2. If the CRCR register is written while the Command Ring is stopped (CRR = 0b), the value of this
field shall be used to fetch the first Command TRB the next time the Host Controller Doorbell
register is written with the dB Reason field set to Host Controller Command.
3. If the CRCR register is not written while the Command Ring is stopped (CRR = 0b), then the
Command Ring shall begin fetching Command TRBs at the current value of the internal xHC
Command Ring Dequeue Pointer.
4. Reading this field always returns 0b.
5:4 Reserved.
3 Command Ring Running (CRR) — RO. This bit is set to 1b if the Run/Stop (R/S) bit is 1b and the
Host Controller Doorbell register is written with the dB Reason field set to Host Controller Command.
It is cleared to 0b when the Command Ring is stopped after writing a 1b to the Command Stop (CS)
or Command Abort (CA) bits, or if the R/S bit is cleared to 0b.
2 Command Abort (CA) — R/W. Writing a 1b to this bit shall immediately terminate the currently
executing command, stop the Command Ring, and generate a Command Completion Event with the
Completion Code set to Command Ring Stopped.
The next write to the Host Controller Doorbell with dB Reason field set to Host Controller Command
shall restart the Command Ring operation.
Notes:
1. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) = 0b.
2. Reading this bit always returns 0b.
1 Command Stop (CS) — R/W. Writing a 1b to this bit shall stop the operation of the Command Ring
after the completion of the currently executing command, and generate a Command Completion
Event with the Completion Code set to Command Ring Stopped and the Command TRB Pointer set to
the current value of the Command Ring Dequeue Pointer.
The next write to the Host Controller Doorbell with dB Reason field set to Host Controller Command
shall restart the Command Ring operation.
Notes:
1. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) bit = 0b.
2. Reading this bit always returns 0b.
0 Ring Cycle State (RCS) — R/W. This bit identifies the value of the xHC Consumer Cycle State
(CCS) flag for the TRB referenced by the Command Ring Pointer.
Notes:
1. Writes to this bit are ignored when the Command Ring Running (CRR) bit = 1b.
2. If the CRCR register is written while the Command Ring is stopped (CCR = 0b), then the value
of this flag shall be used to fetch the first Command TRB the next time the Host Controller
Doorbell register is written with the dB Reason field set to Host Controller Command.
3. If the CRCR register is not written while the Command Ring is stopped (CCR = 0b), then the
Command Ring will begin fetching Command TRBs using the current value of the internal
Command Ring CCS flag.
4. Reading this flag always returns 0b.