Datasheet
xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 445
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.3 PAGESIZE—Page Size Register
Offset: MEM_BASE + 88h–8Bh Attribute: RO
Default Value: 00000001h Size: 32 bits
11.3.2.4 DNCTRL—Device Notification Control Register
Offset: MEM_BASE + 94h–97h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
9 Restore State Status (RSS) ⎯ RO. When the Controller Restore State (CRS) flag in the USB_CMD
register is written with 1b this bit shall be set to 1b and remain set while the xHC restores its internal
state.
Note: When the Restore State operation is complete, this bit shall be cleared to 0b.
8 Save State Status (SSS) ⎯ RO. When the Controller Save State (CSS) flag in the USB_CMD register
is written with 1b this bit shall be set to 1b and remain set while the xHC saves its internal state.
Note: When the Save State operation is complete, this bit shall be cleared to 0b.
7:5 Reserved.
4 Port Change Detect (PCD) — R/WC. This bit is allowed to be maintained in the Auxiliary power
well. Alternatively, it is also acceptable that on a D3 to D0 transition of the xHC, this bit is loaded with
the OR of all of the PORTSC change bits (including: Force port resume, overcurrent change, enable/
disable change and connect status change). Regardless of the implementation, when this bit is
readable (that is, in the D0 state), it must provide a valid view of the Port Status registers.
0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0 to 1 as a
result of a J-K transition detected on a suspended port.
1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is cleared to 0
has a change bit transition from a 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a
result of a J-K transition detected on a suspended port.
3 Event Interrupt (EINT) — R/WC. The xHC sets this bit to 1b when the Interrupt Pending (IP) bit of
any Interrupter is transitions from 0b to 1b.
Software that uses EINT shall clear it prior to clearing any IP flags. A race condition will occur if
software clears the IP flags then clears the EINT flag, and between the operations another IP ‘0’ to '1'
transition occurs. In this case the new IP transition will be lost.
2 Host System Error (HSE)— R/WC. The xHC sets this bit to 1b when a serious error is detected,
either internal to the xHC or during a host system access involving the xHC module. Conditions that
set this bit to ‘1’ include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error
occurs, the xHC clears the Run/Stop (R/S) bit in the USB_CMD register to prevent further execution
of the scheduled TDs. If the HSEE bit in the USB_CMD register is 1b, the xHC shall also assert out-of-
band error signaling to the host.
1 Reserved.
0 HCHalted (HCH) — RO. This bit is a ‘0’ whenever the Run/Stop (R/S) bit is set to 1b. The xHC sets
this bit to 1b after it has stopped executing as a result of the Run/Stop (R/S) bit being cleared to 0b,
either by software or by the xHC hardware (such as internal error).
If this bit is set to1b, then SOFs, microSOFs, or Isochronous Timestamp Packets (ITP) shall not be
generated by the xHC.
Bit Description
Bit Description
31:16 Reserved
15:0 Page Size — RO. Hardwired to 1h to indicate support for 4k byte page sizes.
Bit Description
31:16 Reserved.
15:0 Notification Enable — R/W. When a Notification Enable bit is set, a Device Notification Event will be
generated when a Device Notification Transaction Packet is received with the matching value in the
Notification Type field. For example, setting N1 to ‘1’ enables Device Notification Event generation if
a Device Notification TP is received with its Notification Type field set to ‘1’ (FUNCTION_WAKE), and
so on.
Refer to the USB 3.0 Specification for more information on Notification Types.