Datasheet

xHCI Controller Registers (D20:F0)
444 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.2.2 USB_STS—USB Status Register
Offset: MEM_BASE + 84h–87h Attribute: R/WC, RO
Default Value: 00000001h Size: 32 bits
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in Section 4 of the xHCI specification for additional
information concerning interrupt conditions.
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
2 Interrupter Enable (INTE) — R/W. This bit provides system software with a means of enabling or
disabling the host system interrupts generated by interrupters.
When this bit is set to 1b, then Interrupter host system interrupt generation is allowed, such that the
xHC shall issue an interrupt at the next interrupt threshold if the host system interrupt mechanism
(such that MSI, MSIX, and so on) is enabled. The interrupt is acknowledged by a host system
interrupt specific mechanism.
1 Host Controller Reset (HCRST) — R/W. This control bit is used by software to reset the host
controller.
When software sets this bit to 1b, the Host Controller resets its internal pipelines, timers, counters,
state machines, and so on to their initial value. Any transaction currently in progress on USB is
immediately terminated. A USB reset is not driven on downstream ports.
PCI Configuration registers are not affected by this reset. All operational registers, including port
registers and port state machines are set to their initial values.
Notes:
1. This bit is cleared to 0b by the Host Controller when the reset process is complete. Software
cannot terminate the reset process early by writing a 0b to this bit and shall not write any xHC
Operational or Runtime registers while HCRST is set to 1b.
2. Software shall not set this bit to 1b when the HCHalted (HCH) bit (MEM_BASE+84h:bit 0) is
cleared to 0b. Attempting to reset an actively running host controller will result in undefined
behavior.
0 Run/Stop (R/S) — R/W.
When set to 1b, the xHC proceeds with execution of the schedule. The xHC continues execution as
long as this bit is set to 1b.
When this bit is cleared to 0b, the xHC completes the current and any actively pipelined transactions
on the USB and then halts. The xHC shall halt within 16 microframes after software clears the Run/
Stop bit. The HCHalted (HCH) bit (MEM_BASE+84h:bit 0) indicates when the xHC has finished its
pending pipelined transactions and has entered the stopped state. Software shall not write a ‘1’ to
this flag unless the xHC is in the Halted state (that is, HCH in the USBSTS register is ‘1’); doing so
will yield undefined results.
Bit Description
Bit Description
31:13 Reserved.
12 Host Controller Error (HCE) ⎯ RO. This flag shall be set to indicate that an internal error condition
has been detected which requires software to reset and re-initialize the xHC.
0 = No internal xHC error conditions exist.
1 = Internal xHC error condition exists.
11 Controller Not Ready (CNR) ⎯ RO.
0 = Ready
1 = Not Ready
Software shall not write any Doorbell or Operational register of the xHC, other than the USBSTS
register, until CNR = 0b. This flag is set by the xHC after a Hardware Reset and cleared when the xHC
is ready to begin accepting register writes. This flag shall remain cleared (0b) until the next Chip
Hardware Reset.
10 Save/Restore Error (SRE) ⎯ R/WC. If an error occurs during a Save or Restore operation this bit
shall be set to 1b. This bit shall be cleared to 0b when a Save or Restore operation is initiated or when
written with 1b.