Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 443
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: Software must read and write these registers using only DWord accesses.
11.3.2.1 USB_CMD—USB Command Register
Offset: MEM_BASE + 80h–83h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
484h, 494h,
4A4h, 4B4h,
4C4h, 4D4h,
4E4h, 4F4h,
504h, 514h,
524h, 534h,
544h, 554h,
564h
Multiple PORTPMSCNUSB2 Port N Power Management
Status and Control USB2
00000000h R/W, RO
570h, 580h,
590h, 5A0h,
5B0h, 5C0h
Multiple PORTSCNUSB3 Port N Status and Control
USB3
000002A0h R/W, RO
574h, 584h,
594h, 5A4h,
5B4h, 5C4h
Suspend PORTPMSCN Port N Power Management
Status and Control USB3
00000000h R/W, RO
578h, 588h,
598h, 5A8h,
5B8h, 5C8h
Core PORTLIX USB 3.0 Port Link Info 00000000h RO
Table 11-3. Enhanced Host Controller Operational Register Address Map (Sheet 2 of 2)
MEM_BASE +
Offset
Power Well Mnemonic Register Name Default Type
Bit Description
31:12 Reserved.
11 Enable U3 MFINDEX Stop (EU3S) — R/W.
When set to 1b, the xHC may stop the MFINDEX counting action if all Root Hub ports are in the U3,
Disconnected, Disabled, or Powered-off state.
When cleared to 0b, the xHC may stop the MFINDEX counting action if all Root Hub ports are in the
Disconnected, Disabled, or Powered-off state.
10 Enable Wrap Event (EWE) — R/W.
When set to 1b, the xHC shall generate a MFINDEX Wrap Event every time the MFINDEX register
transitions from 03FFFh to 0.
When cleared to 0b, no MFINDEX Wrap Events are generated.
9 Controller Restore State (CRS) — R/W. When set to 1b, MEM_BASE+80h:bit 0= 0b, and
MEM_BASE+80h:bit 8 = 1b, the xHC shall perform a Restore State operation and restore its internal
state.
When set to 1b and MEM_BASE+80h:bit 0= 1b or MEM_BASE+80h:bit 8 = 0b, or when cleared to
‘0’, no Restore State operation shall be performed.
Note: This flag always returns ‘0’ when read.
8 Controller Save State (CSS) — R/W. When written by software with 1b and MEM_BASE+80h:bit
0= 0b, the xHC shall save any internal state that will be restored by a subsequent Restore State
operation.
When written by software with 1b and MEM_BASE+80h:bit 0= 1b, or written with ‘0’, no Save State
operation shall be performed.
Note: This flag always returns ‘0’ when read.
7 Light Host Controller Reset (LHCRST) — R/W. If the Light HC Reset Capability (LHRC) bit
(MEM_BASE=10h:bit 5) is 1b, then setting this bit to 1b allows the driver to reset the xHC without
affecting the state of the ports.
A system software read of this bit as 0b indicates the Light Host Controller Reset has completed and
it is safe for software to re-initialize the xHC. A software read of this bit as a 1b indicates the Light
Host Controller Reset has not yet completed.
Note: If Light HC Reset Capability is not implemented, a read of this flag will always return a 0b.
6:4 Reserved.
3 Host System Error Enable (HSEE) — R/W. When this bit is set to 1b, and the HSE bit
(MEM_BASE+84h:bit 2) is set to 1b, the xHC shall assert out-of-band error signaling to the host. The
signaling is acknowledged by software clearing the HSE bit.