Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 441
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.1.6 HCCPARAMS—Host Controller Capability Parameters Register
Offset: MEM_BASE + 10h–13h Attribute: RW/L
Default Value: 200071E9h Size: 32 bits
7:0 U1 Device Exit Latency (U1DEL) — RW/L. Worst case latency to transition a root hub Port Link
State (PLS) from U1 to U0. Applies to all root hub ports.
The following are permissible values:
Bit Description
Value Description
00h Zero
01h Less than 1 μs
02h Less than 2 μs
...
0800h-FFFFh Reserved
Bit Description
31:16 xHCI Extended Capabilities Pointer (xECP) — RW/L This field indicates the existence of a
capabilities list. The value of this field indicates a relative offset, in 32-bit words, from Base to the
beginning of the first extended capability.
15:12 Maximum Primary Stream Array Size (MaxPSASize) — RW/L. This fields identifies the
maximum size Primary Stream Array that the xHC supports. The Primary Stream Array size =
2
MaxPSASize+1
. Valid MaxPSASize values are 1 to 15.
11 Reserved.
10 Stopped EDLTA Capability (SEC) — RW/L. This flag indicates that the host controller
implementation Stream Context support a Stopped EDLTA field.
9 Stopped Short Packet Capability (SPC) — RW/L. This flag indicates that the host controller
implementation is capable of generating a Stopped - Short Packet Completion Code.
8 Reserved.
7 No Secondary SID Support (NSS) — RW/L. Hardwired to ‘0’ indicating Secondary Stream ID
decoding is supported.
6 Latency Tolerance Messaging Capability (LTC) — RW/L.
0 = Latency Tolerance Messaging is not supported.
1 = Latency Tolerance Messaging is supported
5 Light HC Reset Capability (LHRC) — RW/L.
0 = Light Host Controller Reset is not supported.
1 = Light Host Controller Reset is supported
4 Port Indicators (PIND) — RW/L. This bit indicates whether the xHC root hub ports support port
indicator control. When this bit is a ‘1’, the port status and control registers include a read/writeable
field for controlling the state of the port indicator.
3 Port Power Control (PPC) — RO. This bit indicates whether the host controller implementation
includes port power control. A ‘1’ in this bit indicates the ports have port power switches. A ‘0’ in this
bit indicates the port do not have port power switches.
2 Context Size (CSZ) — RW/L. If this bit is set to ‘1’, then the xHC uses 64 byte Context data
structures. If this bit is cleared to ‘0’, then the xHC uses 32 byte Context data structures.
Note: This flag does not apply to Stream Contexts.
1 BW Negotiation Capability (BNC) — RW/L.
0 = Not capable of BW Negotiation.
1 = Capable of BW Negotiation.
0 64-bit Addressing Capability (AC64) — RW/L. This bit documents the addressing range capability
of the xHC. The value of this flag determines whether the xHC has implemented the high order 32
bits of 64 bit register and data structure pointer fields. Values for this flag have the following
interpretation:
0 = Supports 32-bit address memory pointers
1 = Supports 64-bit address memory pointers
If 32-bit address memory pointers are implemented, the xHC shall ignore the high order 32 bits of
64 bit data structure pointer fields, and system software shall ignore the high order 32 bits of 64 bit
xHC registers.