Datasheet

xHCI Controller Registers (D20:F0)
440 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.3.1.3 HCSPARAMS1—Host Controller Structural Parameters #1 Register
Offset: MEM_BASE + 04h–07h Attribute: RW/L
Default Value: 15000820h Size: 32 bits
11.3.1.4 HCSPARAMS2—Host Controller Structural Parameters #2 Register
Offset: MEM_BASE + 08h–0Bh Attribute: RW/L
Default Value: 84000054h Size: 32 bits
11.3.1.5 HCSPARAMS3—Host Controller Structural Parameters #3 Register
Offset: MEM_BASE + 0Ch–0Fh Attribute: RW/L
Default Value: 00040001h Size: 32 bits
Bit Description
31:24 Number of Ports (MaxPorts)— RW/L. This field specifies the number of physical downstream ports
implemented on this host controller. The value of this field determines how many port registers are
addressable in the Operational Register Space. Default value = 15h
23:19 Reserved
18:8 Number of Interrupters (MaxIntrs) — RW/L. This field specifies the number of interrupters
implemented on this host controller. Each interrupter is allocated to a vector of MSI and controls its
generation and moderation.
7:0 Number of Device Slots (MaxSlots) — RW/L. This field specifies the number of Device Context
Structures and Doorbell Array entries this host controller can support. Valid values are in the range of
1 to 255.
Bit Description
31:27 Max Scratchpad Buffers (MaxScratchpadBufs) — RW/L. Indicates the number of Scratchpad
Buffers system software shall reserve for the xHC.
26 Scratchpad Restore (SPR) — RW/L.
0 = Indicates the Scratchpad buffer space may be freed and reallocated between power events.
1 = Indicates that the xHC requires the integrity of the Scratchpad buffer space to be maintained
across power events.
25:8 Reserved.
7:4 Event Ring Segment Table Max (ERSTMax): — RW/L. This field determines the maximum value
supported by the Event Ring Segment Table Base Size registers.
3:0 Isochronous Scheduling Threshold (IST) — RW/L. This field indicates to system software the
minimum distance (in time) that it is required to stay ahead of the xHC while adding TRBs, in order
to have the xHC process them at the correct time. The value is specified in the number if frames/
microframes.
If bit [3] of IST is cleared o 0b, software can add a TRB no later than IST [2:0] microframes before
that TRB is scheduled to be executed.
If bit [3] of IST is set to 1b, software can add a TRB no later than IST[2:0] frames before that TRB is
scheduled to be executed.
Bit Description
31:16 U2 Device Exit Latency (U2DEL) — RW/L. Indicates the worst case latency to transition from U2
to U0. Applies to all root hub ports.
The following are permissible values:
15:8 Reserved.
Value Description
00h Zero
01h Less than 1 μs
02h Less than 2 μs
...
0Bh-FFh Reserved