Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 439
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
should not be forwarded to PCI as the address space is known to be allocated to USB.
Attempting to access the xHCI controller Memory-Mapped I/O space using locked
memory transactions will result in undefined behavior.
Note: When the xHCI function is in the D3 PCIe power state, accesses to the xHCI memory
range are ignored and result in a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D20:F0:04h, bit 1) is not set in the Command register in configuration
space, the memory range will not be decoded by Intel® Xeon® Processor D-1500
Product Family xHC. If the MSE bit is not set, Intel® Xeon® Processor D-1500 Product
Family must default to allowing any memory accesses for the range specified in the
BAR to go to PCI. This is because the range may not be valid and, therefore, the cycle
must be made available to any other targets that may be currently using that range.
11.3.1 Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation.
11.3.1.1 CAPLENGTH—Capability Registers Length Register
Offset: MEM_BASE + 00h Attribute: RW/L
Default Value: 80h Size: 8 bits
11.3.1.2 HCIVERSION—Host Controller Interface Version Number Register
Offset: MEM_BASE + 02h–03h Attribute: RO
Default Value: 0100h Size: 16 bits
Table 11-2. Enhanced Host Controller Capability Registers
MEM_BASE +
Offset
Power
Well
Mnemonic Register Default Type
00h Core CAPLENGTH Capabilities Registers Length 80h RW/L
02h–03h Core HCIVERSION Host Controller Interface Version Number 0100h RO
04h–07h Core HCSPARAMS1 Host Controller Structural Parameters #1 15000820h RW/L
08h–0Bh Core HCSPARAMS2 Host Controller Structural Parameters #2 84000054h RW/L
0Ch–0Fh Core HCSPARAMS3 Host Controller Structural Parameters #3 00040001h RW/L
10h–13h Core HCCPARAMS Host Controller Capability Parameters 200071E9h RW/L
14h–17h Core dBOFF Doorbell Offset 0000C000h RO
18h–1Bh Core RTSOFF Runtime Register Space Offset 00001000h RO
Bit Description
7:0 Capability Register Length Value — RW. This register is used as an offset to add to the Memory
Base Register (D20:F0:10h) to find the beginning of the Operational Register Space. This register is
modified and maintained by BIOS.
Bit Description
15:0 Host Controller Interface Version Number — RO. This is a two-byte register containing a BCD
encoding of the version number of interface that this host controller interface conforms to.