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xHCI Controller Registers (D20:F0)

438 Intel® Xeon® Processor D-1500 Product Family

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

11.2.39 USB2PDO—xHCI USB Port Disable Override Register

(USB xHCI—D20:F0)

Address Offset: E4–E7h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

Power Well: Suspend

11.2.40 USB3PDO - USB3 Port Disable Override (USB xHCI—

D20:F0)

Address Offset: E8–EBh Attribute: R/WO

Default Value: 00000000h Size: 32 bits

Power Well: Suspend

11.3 Memory-Mapped I/O Registers

The xHCI memory-mapped I/O space is composed of two sets of registers: Capability

Registers and Operational Registers.

Note: Intel® Xeon® Processor D-1500 Product Family xHC controller will not accept locked

memory transactions (neither reads nor writes) as a target. The locked transactions

5:0 USB 2.0 Host Controller Selector Mask (USB2HCSELM) — R/W. This bit field allows the BIOS to

communicate to the OS which USB 3.0 ports can have the SuperSpeed capabilities enabled.

When set to 1, the OS may enable or disable the SuperSpeed capabilities by modifying the

corresponding USB3PSSEN bit (D20:F0:D8h, bit 3:0).

When cleared to 0, the OS shall not modify the corresponding USB3PSSEN bit.

Bit 0 = USB 3.0 Port 1

Bit 1 = USB 3.0 Port 2

Bit 2 = N/A

Bit 3 = N/A

Bit 4 = USB 3.0 Port 5

Bit 5 = USB 3.0 Port 6

Bit Description

31:15 Reserved.

14:0 xHCI USB Port Disable Override (XUSBPDO) — R/WO.

0 = Allows corresponding USB port to report a Device Connection to the xHC.

1 = Prevents the corresponding USB port from reporting a Device Connection to the xHC.

Port to bit mapping is in one-hot encoding; that is, bit 0 controls port 1 and so on.

Bit 0 = USB 2.0 Port 0

....

Bit 13 = USB 2.0 Port 13